Intel Arria 10 User Manual

Figure 206. Dynamic Reconfiguration of Transmitter Channel During Device Operation
Device Power Up
pll_cal_busy
tx_cal_busy
tx_analogreset
pll_powerdown
pll_locked
tx_digitalreset
1 3
5
2
Legal
Reconfiguration
Window
4
t
req
t
req
t
tx_digitalreset
(1)
t
req
= 70 μs
Note:
(1) The Arria 10 Default setting presets ttx_digitalreset to 70 μs.
(2) Area in gray is don’t care zone.
RX Channel
The numbers in this list correspond to the numbers in the following figure.
1.
Assert rx_analogreset and rx_digitalreset. Ensure that rx_cal_busy is
low. You must reset the PCS by asserting rx_digitalreset every time you
assert rx_analogreset.
2. Perform dynamic reconfiguration after minimum 70 μs of asserting
rx_analogreset.
3.
Deassert rx_analogreset after performing dynamic reconfiguration.
4.
The rx_is_lockedtodata signal goes high after the CDR acquires lock.
5.
Ensure rx_is_lockedtodata is asserted for t
LTD
(minimum of 4 μs) before
deasserting rx_digitalreset.
4. Resetting Transceiver Channels
UG-01143 | 2018.06.15
Intel
®
Arria
®
10 Transceiver PHY User Guide
426

Intel Arria 10 Specifications

General

Transceiver Data Rate	Up to 17.4 Gbps
Transceiver Protocols Supported	CPRI, JESD204B
Transceiver Power Consumption	Varies depending on configuration and data rate. Refer to Intel Arria 10 device power estimation tools.
Transceiver Features	Clock data recovery
Power Consumption per Channel	Varies depending on data rate and equalization settings. Refer to Intel Arria 10 device power estimation tools.
Transceiver Type	FPGA integrated transceiver
Operating Temperature Range	-40°C to 100°C (Industrial)
Number of Transceiver Channels	up to 96 full-duplex