Intel Arria 10 User Manual

Table 17. Enhanced PCS Parameters
Parameter Range Description
Enhanced PCS / PMA
interface width
32, 40, 64 Specifies the interface width between the Enhanced PCS and the
PMA.
FPGA fabric /Enhanced
PCS interface width
32, 40, , 64, 66, 67 Specifies the interface width between the Enhanced PCS and the
FPGA fabric.
The 66-bit FPGA fabric to PCS interface width uses 64-bits from the
TX and RX parallel data. The block synchronizer determines the
block boundary of the 66-bit word, with lower 2 bits from the
control bus.
The 67-bit FPGA fabric to PCS interface width uses the 64-bits from
the TX and RX parallel data. The block synchronizer determines the
block boundary of the 67-bit word with lower 3 bits from the control
bus.
Enable Enhanced PCS
low latency mode
On/Off Enables the low latency path for the Enhanced PCS. When you turn
on this option, the individual functional blocks within the Enhanced
PCS are bypassed to provide the lowest latency path from the PMA
through the Enhanced PCS. When enabled, this mode is applicable
for GX devices. Intel recommends not enabling it for GT devices.
Enable RX/TX FIFO
double width mode
On/Off Enables the double width mode for the RX and TX FIFOs. You can
use double width mode to run the FPGA fabric at half the frequency
of the PCS.
Table 18. Enhanced PCS TX FIFO Parameters
Parameter Range Description
TX FIFO Mode Phase-Compensation
Register
Interlaken
Basic
Fast Register
Specifies one of the following modes:
• Phase Compensation: The TX FIFO compensates for the clock
phase difference between the read clock rx_clkout and the
write clocks tx_coreclkin or tx_clkout. You can tie
tx_enh_data_valid to 1'b1.
•
Register: The TX FIFO is bypassed. The tx_parallel_data,
tx_control and tx_enh_data_valid are registered at the
FIFO output. Assert tx_enh_data_valid port 1'b1 at all
times. The user must connect the write clock tx_coreclkin to
the read clock tx_clkout.
• Interlaken: The TX FIFO acts as an elastic buffer. In this mode,
there are additional signals to control the data flow into the
FIFO. Therefore, the FIFO write clock frequency does not have
to be the same as the read clock frequency. You can control
writes to the FIFO with tx_enh_data_valid. By monitoring
the FIFO flags, you can avoid the FIFO full and empty
conditions. The Interlaken frame generator controls reads.
• Basic: The TX FIFO acts as an elastic buffer. This mode allows
driving write and read side of FIFO with different clock
frequencies. tx_coreclkin or rx_coreclkin must have a
minimum frequency of the lane data rate divided by 66. The
frequency range for tx_coreclkin or rx_coreclkin is (data
rate/32) - (data rate/66). For best results, Intel recommends
that tx_coreclkin or rx_coreclkin = (data rate/32).
Monitor FIFO flag to control write and read operations. For
additional details refer to Enhanced PCS FIFO Operation on page
297 section
• Fast Register: The TX FIFO allows a higher maximum
frequency (f
MAX
) between the FPGA fabric and the TX PCS at the
expense of higher latency.
TX FIFO partially full
threshold
10, 11, 12, 13 Specifies the partially full threshold for the Enhanced PCS TX FIFO.
Enter the value at which you want the TX FIFO to flag a partially
full status.
continued...
2. Implementing Protocols in Arria 10 Transceivers
UG-01143 | 2018.06.15
Intel
®
Arria
®
10 Transceiver PHY User Guide
56

Intel Arria 10 Specifications

General

Transceiver Data Rate	Up to 17.4 Gbps
Transceiver Protocols Supported	CPRI, JESD204B
Transceiver Power Consumption	Varies depending on configuration and data rate. Refer to Intel Arria 10 device power estimation tools.
Transceiver Features	Clock data recovery
Power Consumption per Channel	Varies depending on data rate and equalization settings. Refer to Intel Arria 10 device power estimation tools.
Transceiver Type	FPGA integrated transceiver
Operating Temperature Range	-40°C to 100°C (Industrial)
Number of Transceiver Channels	up to 96 full-duplex