Intel Arria 10 User Manual

Parameter Value Description
Decision Feedback Equalizer
(DFE) Fixed Tap 3 Co-
efficient
radp_dfe_fxtap3_0 to
radp_dfe_fxtap3_127
Selects the co-efficient of the fixed tap 3 of the
Decision Feedback Equalizer (DFE) when
operating in manual mode.
Decision Feedback Equalizer
(DFE) Fixed Tap 4 Co-
efficient
radp_dfe_fxtap4_0 to
radp_dfe_fxtap4_63
Selects the co-efficient of the fixed tap 4 of the
Decision Feedback Equalizer (DFE) when
operating in manual mode.
Decision Feedback Equalizer
(DFE) Fixed Tap 5 Co-
efficient
radp_dfe_fxtap5_0 to
radp_dfe_fxtap5_63
Selects the co-efficient of the fixed tap 5 of the
Decision Feedback Equalizer (DFE) when
operating in manual mode.
Decision Feedback Equalizer
(DFE) Fixed Tap 6 Co-
efficient
radp_dfe_fxtap6_0 to
radp_dfe_fxtap6_31
Selects the co-efficient of the fixed tap 6 of the
Decision Feedback Equalizer (DFE) when
operating in manual mode.
Decision Feedback Equalizer
(DFE) Fixed Tap 7 Co-
efficient
radp_dfe_fxtap7_0 to
radp_dfe_fxtap7_31
Selects the co-efficient of the fixed tap 7 of the
Decision Feedback Equalizer (DFE) when
operating in manual mode.
Decision Feedback Equalizer
(DFE) Fixed Tap 8 Co-
efficient
radp_dfe_fxtap8_0 to
radp_dfe_fxtap8_31
Selects the co-efficient of the fixed tap 8 of the
Decision Feedback Equalizer (DFE) when
operating in manual mode.
Decision Feedback Equalizer
(DFE) Fixed Tap 9 Co-
efficient
radp_dfe_fxtap9_0 to
radp_dfe_fxtap9_31
Selects the co-efficient of the fixed tap 9 of the
Decision Feedback Equalizer (DFE) when
operating in manual mode.
Decision Feedback Equalizer
(DFE) Fixed Tap 10 Co-
efficient
radp_dfe_fxtap10_0 to
radp_dfe_fxtap10_31
Selects the co-efficient of the fixed tap 10 of the
Decision Feedback Equalizer (DFE) when
operating in manual mode.
Decision Feedback Equalizer
(DFE) Fixed Tap 11 Co-
efficient
radp_dfe_fxtap11_0 to
radp_dfe_fxtap11_31
Selects the co-efficient of the fixed tap 11 of the
Decision Feedback Equalizer (DFE) when
operating in manual mode.
On-Chip termination
R_ext0, r_r1, r_r2
Selects the on-chip RX differential termination.
Table 44. Generation Options
Parameter Value Description
Generate parameter
documentation file
On/Off When you turn on this option, generation produces a Comma-
Separated Value (.csv ) file with descriptions of the Transceiver
Native PHY IP parameters.
Related Information
• Analog Parameter Settings on page 585
• XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_PRE_TAP_1T on page 602
• XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_PRE_TAP_2T on page 602
• XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP on page 603
• XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_2ND_POST_TAP on page 604
• Reconfiguration Interface and Dynamic Reconfiguration on page 502
• Transmitter Pre-Emphasis First Pre-Tap Value on page 600
• Transmitter Pre-Emphasis Second Pre-Tap Value on page 600
• Transmitter Pre-Emphasis First Post-Tap Value on page 601
• Transmitter Pre-Emphasis Second Post-Tap Value on page 601
2. Implementing Protocols in Arria 10 Transceivers
UG-01143 | 2018.06.15
Intel
®
Arria
®
10 Transceiver PHY User Guide
72

Intel Arria 10 Specifications

General

Transceiver Data Rate	Up to 17.4 Gbps
Transceiver Protocols Supported	CPRI, JESD204B
Transceiver Power Consumption	Varies depending on configuration and data rate. Refer to Intel Arria 10 device power estimation tools.
Transceiver Features	Clock data recovery
Power Consumption per Channel	Varies depending on data rate and equalization settings. Refer to Intel Arria 10 device power estimation tools.
Transceiver Type	FPGA integrated transceiver
Operating Temperature Range	-40°C to 100°C (Industrial)
Number of Transceiver Channels	up to 96 full-duplex