Renesas RL78 Series User Manual

RL78/F13, F14 CHAPTER 17 LIN/UART MODULE (RLIN3)
R01UH0368EJ0210 Rev.2.10 1186
Dec 10, 2015
(19) LIN/UART ID Buffer Register (LIDBn)
Address: F06D5H
7 6 5 4 3 2 1 0
Value after reset:
0 0 0 0 0 0 0 0
Bit Function R/W
7 to 0 Sets the ID value to be referenced for expansion bit/data comparison or data comparison in
SNOOZE mode.
R/W
When the UEBE bit is 1 (expansion bit operation is enabled) and the UEBDCE bit is 1 (data comparison after expansion bit
detection is enabled) in the LUORn1 register, set the value to be compared with the received data to the LIDBn register.
When the UWC bit is 1 (start of reception from STOP mode is enabled) and the URDCC bit is 1 (comparison of the received
data and the LIDBn register value is enabled in SNOOZE mode) in the LUSCn register, set the value to be compared with
the received data to the LIDBn register.
Set the LIDBn register when the URS bit in the LSTn register is 0 (reception not in progress).

Renesas RL78 Series Specifications

General

Core	RL78
CPU Clock Speed	Up to 32 MHz
Flash Memory	Up to 512 KB
RAM	Up to 32 KB
Operating Voltage	1.6 V to 5.5 V
Low Power Modes	HALT, STOP, SNOOZE
CPU Architecture	16-bit
Temperature Range	-40°C to +85°C
Package	LQFP
Timers	16-bit timers
Communication Interfaces	UART, I2C, LIN
A/D Converter	12-bit