RL78/F13, F14 CHAPTER 17 LIN/UART MODULE (RLIN3)
R01UH0368EJ0210 Rev.2.10 1185
Dec 10, 2015
(18) LIN/UART Data Field Configuration Register (LDFCn)
Address: F06D4H
7 6 5 4 3 2 1 0
— — UTSW — MDL[3:0]
Value after reset:
0 0 0 0 0 0 0 0
Bit Symbol Bit Name Function R/W
3 to 0 MDL[3:0] UART Buffer Data Length Select
b3 b0
0 0 0 0: 9 data
0 0 0 1: 1 data
0 0 1 0: 2 data
0 0 1 1: 3 data
0 1 0 0: 4 data
0 1 0 1: 5 data
0 1 1 0: 6 data
0 1 1 1: 7 data
1 0 0 0: 8 data
1 0 0 1: 9 data
Settings other than the above are prohibited.
R/W
4 — Reserved This bit is always read as 0. The write value should
always be 0.
R/W
5 UTSW Transmission Start Wait 0: When UART buffer transmission is requested,
transmission is started immediately.
1: When UART buffer transmission is requested,
transmission is started after waiting for stop bit
reception to be completed.
R/W
7, 6 — Reserved These bits are always read as 0. The write value should
always be 0.
R/W
MDL[3:0] bits (UART buffer data length select bits)
The MDL bits set the data length of the UART buffer.
Writing a value to these bits is disabled when the RTS bit is 1 (UART buffer transmission is enabled).
UTSW bit (transmission start wait bit)
The UTSW bit controls the start timing of UART buffer transmission.
With 0 set, when UART buffer transmission is requested, transmission is started immediately.
With 1 set, when UART buffer transmission is requested, transmission is started after waiting for reception of the stop bit to
be completed.
Note that the wait time is only 1 bit even if the stop bit length is set to 2 bits with the USBLS bit in the LBFCn register.
This bit is enabled when 1 is set to the RTS bit in the LTRCn register.
Writing a value to this bit is disabled when the RTS bit is 1 (UART buffer transmission is enabled).
Do not set this bit to 1 for the purpose other than switching from reception to transmission in half-duplex communication.
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