Renesas RL78 Series User Manual

RL78/F13, F14 CHAPTER 17 LIN/UART MODULE (RLIN3)
R01UH0368EJ0210 Rev.2.10 1184
Dec 10, 2015
EXBT flag (expansion bit detection flag)
Only 0 can be written to the EXBT flag; when 1 is written, the bit retains the value that has been retained before 1 is written.
This flag is set to 1 when the UEBE bit in the LUORn1 register is 1 (expansion bit operation is enabled) and the received
expansion bit agrees with the UEBDL bit value in the LUORn1 register.
In SNOOZE mode, the following conditions should also be satisfied to set this flag to 1.
 The UWC bit in the LUSCn register is 1 (start of reception from STOP mode is enabled).
 The USEC bit in the LUSCn register is 0 (error detection interrupt generation is enabled).
 The UECD bit in the LUORn1 register is 0 (comparison of the expansion bit is enabled).
To clear the bit to 0, write 0 to the bit.
IDMT flag (ID match flag)
Only 0 can be written to the IDMT flag; when 1 is written, the bit retains the value that has been retained before 1 is written.
The IDMT flag is set to 1 when all the following conditions are satisfied.
 The UEBE bit in the LUORn1 register is 1 (expansion bit operation is enabled).
 The UECD bit in the LUORn1 register is 0 (expansion bit comparison is enabled).
 The UEBDCE bit in the LUORn1 register is 1 (data comparison after expansion bit detection is enabled).
 The received expansion bit agrees with the value of the UEBDL bit in the LUORn1 register.
 The 8-bit received data excluding the expansion bits agrees with the LIDBn register value.
To clear the bit to 0, write 0 to the bit.
UPER flag (parity error flag)
Only 0 can be written to the IDMT flag; when 1 is written, the bit retains the value that has been retained before 1 is written.
The UPER flag is set to 1 upon parity error detection.
In SNOOZE mode, the following conditions should also be satisfied to set this flag to 1.
 The UWC bit in the LUSCn register is 1 (start of reception from STOP mode is enabled).
 The USEC bit in the LUSCn register is 0 (error detection interrupt generation is enabled).
To clear the bit to 0, write 0 to the bit.

Renesas RL78 Series Specifications

General

Core	RL78
CPU Clock Speed	Up to 32 MHz
Flash Memory	Up to 512 KB
RAM	Up to 32 KB
Operating Voltage	1.6 V to 5.5 V
Low Power Modes	HALT, STOP, SNOOZE
CPU Architecture	16-bit
Temperature Range	-40°C to +85°C
Package	LQFP
Timers	16-bit timers
Communication Interfaces	UART, I2C, LIN
A/D Converter	12-bit