Renesas RL78 Series User Manual

RL78/F13, F14 CHAPTER 17 LIN/UART MODULE (RLIN3)
R01UH0368EJ0210 Rev.2.10 1232
Dec 10, 2015
(4) Transmission Start Wait Function
For performing half-duplex communication, the LIN/UART module (in UART mode) has the function of securing the reception
stop bit when switching from reception to transmission.
If it is desired to delay the start of transmission until the stop bits for the reception are completed, set data in the LUWTDRn
register, which is used only for the wait function, instead of setting transmission data in the LUTDRn register as a start-of-
transmission request. When transmitting from the UART buffer, set 1 (UART buffer transmission enabled) in the RST bit in
the LTRCn register with 1 set in the UTSW bit in the LDFCn register.
In such a case, the LIN/UART module delays the start of transmission until the stop bits of reception data are completed.
It should be noted that even if the UART stop bit length select bit (USBLS) is 1 (stop bits = 2 bits), delay is made only for 1
bits.
Figure 17-31 shows the operation of transmission wait function.
Figure 17-31. Transmission Wait Function (if transmission data is set during the stop bits in the received data)
Stop bit length is shortened in switching from reception to
transmission when transmission start wait function is not used.
LTXDn Start bit Bit 0
Transmit bit enable
(internal signal)
LRXDn Start bit
Bit 0
Stop bit Start bit Bit 0
Sampling point
(internal signal)
Receive bit end
(internal signal)
Stop bit length (one bit) is not shortened in switching from reception to
transmission when transmission start wait function is used.
LTXDn
Start bit Bit 0
Transmit bit enable
(internal signal)
LRXDn Start bit Bit 0 Stop bit
Start bit
Bit 0
Sampling point
(internal signal)
Receive bit end
(internal signal)
Set transmission data in LUTDRn register,
or
set RTS bit to 1 with UTSW bit = 0.
Stop bit length is shortened.
Set transmission data in LUWTDRn register,
or
set RTS bit to 1 with UTSW bit = 1.
Stop bit length (one bit) is not shortened.
After issuance of a transmission
trigger and high to low transition
of the reception bit end signal,
transmission is started at the
next transmission bit enable
signal assertion.

Renesas RL78 Series Specifications

General

Core	RL78
CPU Clock Speed	Up to 32 MHz
Flash Memory	Up to 512 KB
RAM	Up to 32 KB
Operating Voltage	1.6 V to 5.5 V
Low Power Modes	HALT, STOP, SNOOZE
CPU Architecture	16-bit
Temperature Range	-40°C to +85°C
Package	LQFP
Timers	16-bit timers
Communication Interfaces	UART, I2C, LIN
A/D Converter	12-bit