Renesas RL78 Series User Manual

RL78/F13, F14 CHAPTER 26 VOLTAGE DETECTOR
R01UH0368EJ0210 Rev.2.10 1574
Dec 10, 2015
Figure 26-6. Timing of Voltage Detector Reset Signal and Interrupt Signal Generation
(Option Byte LVIMDS1, LVIMDS0 = 1, 0) (2/2)
(Notes and Remark are listed on the next page.)
INTLVI
V
POR
= 1.56 V (TYP.)
V
PDR
= 1.55 V (TYP.)
Time
H
V
LVDL
V
LVDH
Supply voltage (V DD )
LVIMK flag
(set by software)
Note 1
Cleared by
software
Cleared by software
RESET
Operation status
LVIF flag
LVISEN flag
(set by software)
LVIOMSK flag
LVIMD flag
LVIRF flag
LVILV flag
LVD reset signal
POR reset signal
Internal reset signal
LVIIF flag
Normal
operation
Save
processing
RESET
Normal operation
RESET
Cleared
Cleared
Note 3
Cleared by
software
Cleared by
software
Note 2
Save processing
When a condition of V
DD is V DD < V LVDH after releasing the mask,
a reset is generated because of LVIMD = 1 (reset mode).
Wait for stabilization by software
(400 μs or 5 clocks of f
IL )
Note 3

Renesas RL78 Series Specifications

General

Core	RL78
CPU Clock Speed	Up to 32 MHz
Flash Memory	Up to 512 KB
RAM	Up to 32 KB
Operating Voltage	1.6 V to 5.5 V
Low Power Modes	HALT, STOP, SNOOZE
CPU Architecture	16-bit
Temperature Range	-40°C to +85°C
Package	LQFP
Timers	16-bit timers
Communication Interfaces	UART, I2C, LIN
A/D Converter	12-bit