RL78/F13, F14 CHAPTER 27 SAFETY FUNCTIONS
R01UH0368EJ0210 Rev.2.10 1595
Dec 10, 2015
<Bit error detection interrupt>
When a bit error is detected, an interrupt request signal (INTRAM) is generated, and the address of the bit error is held in
the error address store register (ERADR). If the bit error is 2 bits, the bit error detection flag (DBERR) in the bit error detection
register (ECCER) is set to 1.
The 1-bit error detection interrupt enable register (ECCIER) can be used to specify whether to output or not an interrupt
request signal when the bit error is 1 bit.
Since the CPU of the RL78 pre-reads the instruction code, RAM fetch area + 10 bytes should be initialized to perform RAM
fetch.
Even when a bit error is detected by reading instruction code, an interrupt request is not generated. Thus, the address that
causes the bit error cannot be known.
<ECC test function>
The following two modes can be selected by the ECC test mode register (ECCTMDR).
Normal operating mode
Test mode (bit error correction function test)
The ECC test mode register should be accessed after the protection by the ECC test protect register (ECCTPR) is cancelled.
Inverting the bit may significantly affect operation of the stack. The bit must thus only be inverted at times such as power-on
so that it has no effect on the application.
For data read from the RAM, the existence of a bit error is detected in the 8-bit read data, 4-bit ECC code, and 1-bit parity
bit.
If a bit error exists, an interrupt request is output and the address of the bit error is stored in the register. If the bit error is 1
bit, the data is corrected.
(a) Normal operating mode
For data write, a 4-bit ECC code is generated using 8-bit write data, and a 1-bit parity bit is generated using the write data
and the ECC code. The generated data is written to the RAM as 13-bit data.
For data read, the existence of a bit error is detected in the 8-bit read data, 4-bit ECC code, and 1-bit parity bit. If the bit
error is 1 bit, the data is corrected and then read.
(b) Test mode (bit error correction function test)
For data write, an ECC code is generated using write data, and a parity bit is generated using the write data and the ECC
code. A given bit value of the 13-bit write data is inverted by the write data inversion register (ECCDWRVR), and the data is
written to the RAM.
For data read, the existence of a bit error is detected in the read data, ECC code, and parity bit. If the bit error is 1 bit, the
data is corrected and then read.
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