Renesas RL78 Series User Manual

Index-16
CHAPTER 18 CAN INTERFACE (RS-CAN LITE) .............................................................................. 1259
18.1 Overview .................................................................................................................................. 1259
18.2 Input/Output Pins ................................................................................................................... 1262
18.3 Register Descriptions ............................................................................................................ 1263
18.3.1 CANi Bit Configuration Register L (CiCFGL) (i = 0) .................................................................... 1285
18.3.2 CANi Bit Configuration Register H (CiCFGH) (i = 0) ................................................................... 1286
18.3.3 CANi Control Register L (CiCTRL) (i = 0) ................................................................................... 1288
18.3.4 CANi Control Register H (CiCTRH) (i = 0) .................................................................................. 1290
18.3.5 CANi Status Register L (CiSTSL) (i = 0) ..................................................................................... 1292
18.3.6 CANi Status Register H (CiSTSH) (i = 0) ................................................................................... 1294
18.3.7 CANi Error Flag Register L (CiERFLL) (i = 0) ............................................................................. 1295
18.3.8 CANi Error Flag Register H (CiERFLH) (i = 0) ........................................................................... 1298
18.3.9 CAN Global Configuration Register L (GCFGL) ......................................................................... 1299
18.3.10 CAN Global Configuration Register H (GCFGH) ...................................................................... 1301
18.3.11 CAN Global Control Register L (GCTRL) ................................................................................. 1302
18.3.12 CAN Global Control Register H (GCTRH) ................................................................................ 1303
18.3.13 CAN Global Status Register (GSTS) ........................................................................................ 1304
18.3.14 CAN Global Error Flag Register (GERFLL) .............................................................................. 1305
18.3.15 CAN Global Transmit Interrupt Status Register (GTINTSTS) ................................................... 1306
18.3.16 CAN Timestamp Register (GTSC) ........................................................................................... 1307
18.3.17 CAN Receive Rule Number Configuration Register (GAFLCFG) ............................................. 1308
18.3.18 CAN Receive Rule Entry Register jAL (GAFLIDLj) (j = 0 to 15) ............................................... 1309
18.3.19 CAN Receive Rule Entry Register jAH (GAFLIDHj) (j = 0 to 15) .............................................. 1310
18.3.20 CAN Receive Rule Entry Register jBL (GAFLMLj) (j = 0 to 15) ................................................ 1311
18.3.21 CAN Receive Rule Entry Register jBH (GAFLMHj) (j = 0 to 15) ............................................... 1312
18.3.22 CAN Receive Rule Entry Register jCL (GAFLPLj) (j = 0 to 15) ................................................ 1313
18.3.23 CAN Receive Rule Entry Register jCH (GAFLPHj) (j = 0 to 15) ............................................... 1314
18.3.24 CAN Receive Buffer Number Configuration Register (RMNB) ................................................. 1315
18.3.25 CAN Receive Buffer Receive Complete Flag Register (RMND0) ............................................. 1316
18.3.26 CAN Receive Buffer Register nAL (RMIDLn) (n = 0 to 15) ....................................................... 1317
18.3.27 CAN Receive Buffer Register nAH (RMIDHn) (n = 0 to 15) ...................................................... 1318
18.3.28 CAN Receive Buffer Register nBL (RMTSn) (n = 0 to 15) ........................................................ 1319
18.3.29 CAN Receive Buffer Register nBH (RMPTRn) (n = 0 to 15) ..................................................... 1320
18.3.30 CAN Receive Buffer Register nCL (RMDF0n) (n = 0 to 15) ..................................................... 1321
18.3.31 CAN Receive Buffer Register nCH (RMDF1n) (n = 0 to 15) ..................................................... 1322
18.3.32 CAN Receive Buffer Register nDL (RMDF2n) (n = 0 to 15) ..................................................... 1323
18.3.33 CAN Receive Buffer Register nDH (RMDF3n) (n = 0 to 15) ..................................................... 1324
18.3.34 CAN Receive FIFO Control Register m (RFCCm) (m = 0, 1) ................................................... 1325
18.3.35 CAN Receive FIFO Status Register m (RFSTSm) (m = 0, 1) ................................................... 1327
18.3.36 CAN Receive FIFO Pointer Control Register m (RFPCTRm) (m = 0, 1) .................................. 1329
18.3.37 CAN Receive FIFO Access Register mAL (RFIDLm) (m = 0, 1)............................................... 1330

Renesas RL78 Series Specifications

General

Core	RL78
CPU Clock Speed	Up to 32 MHz
Flash Memory	Up to 512 KB
RAM	Up to 32 KB
Operating Voltage	1.6 V to 5.5 V
Low Power Modes	HALT, STOP, SNOOZE
CPU Architecture	16-bit
Temperature Range	-40°C to +85°C
Package	LQFP
Timers	16-bit timers
Communication Interfaces	UART, I2C, LIN
A/D Converter	12-bit