Renesas RL78 Series User Manual

Index-17
18.3.38 CAN Receive FIFO Access Register mAH (RFIDHm) (m = 0, 1) ............................................. 1331
18.3.39 CAN Receive FIFO Access Register mBL (RFTSm) (m = 0, 1)............................................... 1332
18.3.40 CAN Receive FIFO Access Register mBH (RFPTRm) (m = 0, 1) ............................................ 1333
18.3.41 CAN Receive FIFO Access Register mCL (RFDF0m) (m = 0, 1) ............................................. 1334
18.3.42 CAN Receive FIFO Access Register mCH (RFDF1m) (m = 0, 1) ............................................. 1335
18.3.43 CAN Receive FIFO Access Register mDL (RFDF2m) (m = 0, 1) ............................................. 1336
18.3.44 CAN Receive FIFO Access Register mDH (RFDF3m) (m = 0, 1) ............................................. 1337
18.3.45 CANi Transmit/Receive FIFO Control Register kL (CFCCLk) (i = 0) (k = 0) ............................. 1338
18.3.46 CANi Transmit/Receive FIFO Control Register kH (CFCCHk) (i = 0) (k = 0) ............................ 1340
18.3.47 CANi Transmit/Receive FIFO Status Register k (CFSTSk) (i = 0) (k = 0) ................................. 1342
18.3.48 CANi Transmit/Receive FIFO Pointer Control Register k (CFPCTRk) (i = 0) (k = 0) ................ 1344
18.3.49 CANi Transmit/Receive FIFO Access Register kAL (CFIDLk) (i = 0) (k = 0) ............................ 1345
18.3.50 CANi Transmit/Receive FIFO Access Register kAH (CFIDHk) (i = 0) (k = 0) ........................... 1346
18.3.51 CANi Transmit/Receive FIFO Access Register kBL (CFTSk) (i = 0) (k = 0) ............................. 1347
18.3.52 CANi Transmit/Receive FIFO Access Register kBH (CFPTRk) (i = 0) (k = 0) .......................... 1348
18.3.53 CANi Transmit/Receive FIFO Access Register kCL (CFDF0k) (i = 0) (k = 0) ........................... 1349
18.3.54 CANi Transmit/Receive FIFO Access Register kCH (CFDF1k) (i = 0) (k = 0) .......................... 1350
18.3.55 CANi Transmit/Receive FIFO Access Register kDL (CFDF2k) (i = 0) (k = 0) ........................... 1351
18.3.56 CANi Transmit/Receive FIFO Access Register kDH (CFDF3k) (i = 0) (k = 0) .......................... 1352
18.3.57 Receive FIFO Message Lost Status Register (RFMSTS)......................................................... 1353
18.3.58 CANi Transmit/Receive FIFO Message Lost Status Register (CFMSTS) (i = 0) ...................... 1354
18.3.59 CAN Receive FIFO Interrupt Status Register (RFISTS) ........................................................... 1355
18.3.60 CAN Transmit/Receive FIFO Receive Interrupt Status Register (CFISTS) .............................. 1356
18.3.61 CANi Transmit Buffer Control Register p (TMCp) (i = 0) (p = 0 to 3) ........................................ 1357
18.3.62 CANi Transmit Buffer Status Register p (TMSTSp) (i = 0) (p = 0 to 3) ..................................... 1359
18.3.63 CANi Transmit Buffer Transmit Request Status Register (TMTRSTS) (i = 0) .......................... 1360
18.3.64 CANi Transmit Buffer Transmit Complete Status Register (TMTCSTS) (i = 0)......................... 1361
18.3.65 CANi Transmit Buffer Transmit Abort Status Register (TMTASTS) (i = 0) ............................... 1362
18.3.66 CANi Transmit Buffer Interrupt Enable Register (TMIEC) (i = 0) .............................................. 1363
18.3.67 CANi Transmit Buffer Register pAL (TMIDLp) (i = 0) (p = 0 to 3) ............................................. 1364
18.3.68 CANi Transmit Buffer Register pAH (TMIDHp) (i = 0) (p = 0 to 3) ............................................ 1365
18.3.69 CANi Transmit Buffer Register pBH (TMPTRp) (i = 0) (p = 0 to 3) ........................................... 1366
18.3.70 CANi Transmit Buffer Register pCL (TMDF0p) (i = 0) (p = 0 to 3) ............................................ 1367
18.3.71 CANi Transmit Buffer Register pCH (TMDF1p) (i = 0) (p = 0 to 3) ........................................... 1368
18.3.72 CANi Transmit Buffer Register pDL (TMDF2p) (i = 0) (p = 0 to 3) ............................................ 1369
18.3.73 CANi Transmit Buffer Register pDH (TMDF3p) (i = 0) (p = 0 to 3) ........................................... 1370
18.3.74 CANi Transmit History Buffer Control Register (THLCCi) (i = 0) .............................................. 1371
18.3.75 CANi Transmit History Buffer Status Register (THLSTSi) (i = 0) .............................................. 1372
18.3.76 CANi Transmit History Buffer Access Register (THLACCi) (i = 0) ............................................ 1373
18.3.77 CANi Transmit History Buffer Pointer Control Register (THLPCTRi) (i = 0) ............................. 1374
18.3.78 CAN Global RAM Window Control Register (GRWCR) ............................................................ 1375

Renesas RL78 Series Specifications

General

Core	RL78
CPU Clock Speed	Up to 32 MHz
Flash Memory	Up to 512 KB
RAM	Up to 32 KB
Operating Voltage	1.6 V to 5.5 V
Low Power Modes	HALT, STOP, SNOOZE
CPU Architecture	16-bit
Temperature Range	-40°C to +85°C
Package	LQFP
Timers	16-bit timers
Communication Interfaces	UART, I2C, LIN
A/D Converter	12-bit