Renesas RL78 Series User Manual

Index-19
CHAPTER 19 DTC ............................................................................................................................... 1426
19.1 Overview .................................................................................................................................. 1426
19.2 Registers ................................................................................................................................. 1428
19.2.1 Allocation of DTC Control Data Area and DTC Vector Table Area ............................................. 1430
19.2.2 DTC Control Data Allocation ...................................................................................................... 1431
19.2.3 DTC Vector Table ....................................................................................................................... 1432
19.2.4 Peripheral enable register 1 (PER1) ........................................................................................... 1436
19.2.5 DTC Activation Enable Register i (DTCENi) (i = 0 to 5) .............................................................. 1437
19.2.6 DTC Base Address Register (DTCBAR) .................................................................................... 1440
19.2.7 DTC Control Register j (DTCCRj) (j = 0 to 23) ........................................................................... 1441
19.2.8 DTC Block Size Register j (DTBLSj) (j = 0 to 23) ....................................................................... 1442
19.2.9 DTC Transfer Count Register j (DTCCTj) (j = 0 to 23) ................................................................ 1442
19.2.10 DTC Transfer Count Reload Register j (DTRLDj) (j = 0 to 23) ................................................. 1443
19.2.11 DTC Source Address Register j (DTSARj) (j = 0 to 23) ............................................................ 1443
19.2.12 DTC Destination Address Register j (DTDARj) (j = 0 to 23) ..................................................... 1443
19.2.13 High-speed DTC Channel Select Register 0 (SELHS0) ........................................................... 1444
19.2.14 High-speed DTC Channel Select Register 1 (SELHS1) ........................................................... 1445
19.2.15 High-speed DTC Control Register m (HDTCCR0/1) (m = 0, 1) ................................................ 1446
19.2.16 High-speed DTC Transfer Count Register m (HDTCCT0/1) (m = 0, 1) .................................... 1447
19.2.17 DTC Transfer Count Reload Register m (HDTRLD0/1) (m = 0, 1) ........................................... 1448
19.2.18 High-speed DTC Source Address Register m (HDTSAR0/1) (m = 0, 1) ................................... 1448
19.2.19 High-speed DTC Destination Address Register m (HDTDAR0/1) (m = 0, 1) ............................ 1448
19.3 Operation ................................................................................................................................. 1449
19.3.1 Activation Sources ...................................................................................................................... 1449
19.3.2 Normal Mode .............................................................................................................................. 1451
19.3.3 Repeat Mode .............................................................................................................................. 1453
19.3.4 Chain Transfers .......................................................................................................................... 1457
19.3.5 High-Speed Transfer Operation ................................................................................................. 1459
19.4 Notes on DTC .......................................................................................................................... 1460
19.4.1 Setting DTC Registers and Vector Table.................................................................................... 1460
19.4.2 Allocation of DTC Control Data Area and DTC Vector Table Area ............................................. 1460
19.4.3 DTC Pending Instruction ............................................................................................................ 1461
19.4.4 Operations when an Instruction which Accesses an SFR Register that Requires a Wait is
Executed ..................................................................................................................................... 1461
19.4.5 Operation when Accessing Data Flash Memory Space ............................................................. 1461
19.4.6 Number of DTC Execution Clock Cycles .................................................................................... 1462
19.4.7 Number of High-speed DTC Execution Clock Cycles ................................................................. 1463
19.4.8 DTC Response Time .................................................................................................................. 1464
19.4.9 DTC Activation Sources ............................................................................................................. 1464
19.4.10 Operation in Standby Mode Status ........................................................................................... 1465
19.4.11 Notes When the RAM Area Is the Source of the Data for Transfer .......................................... 1465

Renesas RL78 Series Specifications

General

Core	RL78
CPU Clock Speed	Up to 32 MHz
Flash Memory	Up to 512 KB
RAM	Up to 32 KB
Operating Voltage	1.6 V to 5.5 V
Low Power Modes	HALT, STOP, SNOOZE
CPU Architecture	16-bit
Temperature Range	-40°C to +85°C
Package	LQFP
Timers	16-bit timers
Communication Interfaces	UART, I2C, LIN
A/D Converter	12-bit