Renesas RL78 Series User Manual

Index-20
19.4.12 Vector Address for High-Speed Transfer .................................................................................. 1465
CHAPTER 20 EVENT LINK CONTROLLER (ELC) (RL78/F14 Only) ............................................... 1466
20.1 Overview .................................................................................................................................. 1466
20.2 Registers ................................................................................................................................. 1467
20.2.1 Event Output Destination Select Register n (ELSELRn) (n = 00 to 25) ...................................... 1468
20.2.2 Timer input select register 0 ....................................................................................................... 1471
20.2.3 A/D converter mode register 1 (ADM1) ...................................................................................... 1471
20.2.4 D/A converter mode register (DAM) ........................................................................................... 1471
20.3 Operation ................................................................................................................................. 1472
CHAPTER 21 INTERRUPT FUNCTIONS ........................................................................................... 1473
21.1 Interrupt Function Types ....................................................................................................... 1473
21.2 Interrupt Sources and Configuration ................................................................................... 1474
21.3 Registers Controlling Interrupt Functions ........................................................................... 1484
21.3.1 Interrupt request flag registers (IF0L, IF0H, IF1L, IF1H, IF2L, IF2H, IF3L) ................................ 1490
21.3.2 Interrupt mask flag registers (MK0L, MK0H, MK1L, MK1H, MK2L, MK2H, MK3L) ..................... 1492
21.3.3 Priority specification flag registers (PR00L, PR00H, PR01L, PR01H, PR02L, PR02H, PR03L,
PR10L, PR10H, PR11L, PR11H, PR12L, PR12H, PR13L) ........................................................ 1494
21.3.4 External interrupt rising edge enable registers (EGP0, EGP1),
external interrupt falling edge enable registers (EGN0, EGN1) .................................................. 1497
21.3.5 Interrupt source determination flag register 0 (INTFLG0) ........................................................... 1499
21.3.6 Interrupt mask register (INTMSK) ............................................................................................... 1502
21.3.7 Input switch control register (ISC) .............................................................................................. 1503
21.3.8 Program status word (PSW) ....................................................................................................... 1504
21.4 Interrupt Servicing Operations ............................................................................................. 1505
21.4.1 Maskable interrupt request acknowledgment ............................................................................. 1505
21.4.2 Software interrupt request acknowledgment .............................................................................. 1508
21.4.3 Multiple interrupt servicing .......................................................................................................... 1508
21.4.4 Interrupt servicing during division instruction .............................................................................. 1512
21.4.5 Interrupt request hold ................................................................................................................. 1514
CHAPTER 22 KEY INTERRUPT FUNCTION ................................................................................... 1515
22.1 Functions of Key Interrupt .................................................................................................... 1515
22.2 Configuration of Key Interrupt .............................................................................................. 1516
22.3 Register Controlling Key Interrupt ....................................................................................... 1517
22.3.1 Key return mode register (KRM) ................................................................................................. 1517
CHAPTER 23 STANDBY FUNCTION ................................................................................................ 1518
23.1 Standby Function and Configuration ................................................................................... 1518

Renesas RL78 Series Specifications

General

Core	RL78
CPU Clock Speed	Up to 32 MHz
Flash Memory	Up to 512 KB
RAM	Up to 32 KB
Operating Voltage	1.6 V to 5.5 V
Low Power Modes	HALT, STOP, SNOOZE
CPU Architecture	16-bit
Temperature Range	-40°C to +85°C
Package	LQFP
Timers	16-bit timers
Communication Interfaces	UART, I2C, LIN
A/D Converter	12-bit