Renesas RL78 Series User Manual

RL78/F13, F14 CHAPTER 15 SERIAL ARRAY UNIT
R01UH0368EJ0210 Rev.2.10 850
Dec 10, 2015
Figure 15-38. Flowchart of Master Reception (in Single-Reception Mode)
Remark m: Unit number (m = 0, 1), n: Channel number (n = 0, 1), p: CSI number (p = 00, 01, 10, 11),
mn = 00, 01, 10, 11
Starting CSI communication
Port manipulation
Setting the SAU1EN and
SAU0EN bits of the PER0 register to 1
Setting transfer rate with the SPSm
register
No
Writing 1 to the SSmn bit
Writing dummy data to
the SDRmn register
Transfer end interrupt
generated?
Reading the SDRmn register
Setting the SAU1EN and SAU0EN bits
of the PER0 register to 0
End of communication
No
Starting reception
Reception completed?
Writing 1 to the STmn bit
Yes
Yes
SMRmn, SCRmn: Setting communication
SDRmn[15:9]: Setting transfer rate
SOm: Setting SCKp output
Specify the initial settings while the SEmn bit is
0.

Renesas RL78 Series Specifications

General

Core	RL78
CPU Clock Speed	Up to 32 MHz
Flash Memory	Up to 512 KB
RAM	Up to 32 KB
Operating Voltage	1.6 V to 5.5 V
Low Power Modes	HALT, STOP, SNOOZE
CPU Architecture	16-bit
Temperature Range	-40°C to +85°C
Package	LQFP
Timers	16-bit timers
Communication Interfaces	UART, I2C, LIN
A/D Converter	12-bit