General-purpose timers (TIM2/TIM3/TIM4/TIM5) RM0351
1048/1830 DocID024597 Rev 5
31.4.19 TIM2 option register 1 (TIM2_OR1)
Address offset: 0x50
Reset value: 0x0000
31.4.20 TIM3 option register 1 (TIM3_OR1)
Address offset: 0x50
Reset value: 0x0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
1514131211109876543210
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. TI4_RMP[1:0]
ETR1_
RMP
ITR1_
RMP
rw rw rw rw
Bits 31:4 Reserved, must be kept at reset value.
Bits 3:2 TI4_RMP[1:0]: Input Capture 4 remap
00: TIM2 input capture 4 is connected to I/O
01: TIM2 input capture 4 is connected to COMP1_OUT
10: TIM2 input capture 4 is connected to COMP2_OUT
11: TIM2 input capture 4 is connected to logical OR between COMP1_OUT and
COMP2_OUT
Bit 1 ETR1_RMP: External trigger remap
0: TIM2_ETR is connected to I/O
1: TIM2_ETR is connected to LSE
Bit 0 ITR1_RMP: Internal trigger 1 remap
0: TIM2_ITR1 is connected to TIM8_TRGO
1: TIM2_ITR1 is connected to OTG_FS SOF
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
1514131211109876543210
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. TI1_RMP[1:0]
rw rw
Bits 31:2 Reserved, must be kept at reset value.
Bits 1:0 TI1_RMP[1:0]: Input Capture 1 remap
00: TIM3 input capture 1 is connected to I/O
01: TIM3 input capture 1 is connected to COMP1_OUT
10: TIM3 input capture 1 is connected to COMP2_OUT
11: TIM3 input capture 1 is connected to logical OR between COMP1_OUT and
COMP2_OUT
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