ST STM32L4 5 Series - Figure 287. Counter Timing Diagram, Internal Clock Divided by 2; Figure 288. Counter Timing Diagram, Internal Clock Divided by 4, Timx_Arr=0 X36

General-purpose timers (TIM2/TIM3/TIM4/TIM5) RM0351
994/1830 DocID024597 Rev 5
Figure 287. Counter timing diagram, internal clock divided by 2
Figure 288. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36
1. Center-aligned mode 2 or 3 is used with an UIF on overflow.
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