Flexible static memory controller (FSMC) RM0351
434/1830 DocID024597 Rev 5
Table 77. FMC_BCRx bit fields
Bit number Bit name Value to set
31:22 Reserved 0x000
21 WFDIS
As needed (this bit is reserved for STM32L475xx/476xx/486xx
devices)
20 CCLKEN As needed
19 CBURSTRW 0x0 (no effect in asynchronous mode)
18:16 CPSIZE 0x0 (no effect in asynchronous mode)
15 ASYNCWAIT Set to 1 if the memory supports this feature. Otherwise keep at 0.
14 EXTMOD 0x1 for mode B, 0x0 for mode 2
13 WAITEN 0x0 (no effect in asynchronous mode)
12 WREN As needed
11 WAITCFG Don’t care
10 Reserved 0x0
9 WAITPOL Meaningful only if bit 15 is 1
8 BURSTEN 0x0
7 Reserved 0x1
6 FACCEN 0x1
5:4 MWID As needed
3:2 MTYP 0x2 (NOR Flash memory)
1 MUXEN 0x0
0 MBKEN 0x1
Table 78. FMC_BTRx bit fields
Bit number Bit name Value to set
31:30 Reserved 0x0
29:28 ACCMOD 0x1 if extended mode is set
27:24 DATLAT Don’t care
23:20 CLKDIV Don’t care
19:16 BUSTURN Time between NEx high to NEx low (BUSTURN HCLK).
15:8 DATAST
Duration of the access second phase (DATAST HCLK cycles) for
read accesses.
7:4 ADDHLD Don’t care
3:0 ADDSET
Duration of the access first phase (ADDSET HCLK cycles) for read
accesses. Minimum value for ADDSET is 0.
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