Digital camera interface (DCMI) RM0351
652/1830 DocID024597 Rev 5
20.4.4 Synchronization
The digital camera interface supports embedded or hardware (DCMI_HSYNC and
DCMI_VSYNC) synchronization. When embedded synchronization is used, it is up to the
digital camera module to make sure that the 0x00 and 0xFF values are used ONLY for
synchronization (not in data). Embedded synchronization codes are supported only for the
8-bit parallel data interface width (that is, in the DCMI_CR register, the EDM[1:0] bits should
be cleared to “00”).
For compressed data, the DCMI supports only the hardware synchronization mode. In this
case, DCMI_VSYNC is used as a start/end of the image, and DCMI_HSYNC is used as a
Data Valid signal. Figure 149 shows the corresponding timing diagram.
Figure 149.Timing diagram
Hardware synchronization mode
In hardware synchronization mode, the two synchronization signals
(DCMI_HSYNC/DCMI_VSYNC) are used.
Depending on the camera module/mode, data may be transmitted during horizontal/vertical
synchronization periods. The DCMI_HSYNC/DCMI_VSYNC signals act like blanking
signals since all the data received during DCMI_HSYNC/DCMI_VSYNC active periods are
ignored.
In order to correctly transfer images into the DMA/RAM buffer, data transfer is synchronized
with the DCMI_VSYNC signal. When the hardware synchronization mode is selected, and
Table 131.Positioning of captured data bytes in 32-bit words (14-bit width)
Byte address 31:30 29:16 15:14 13:0
00D
n+1
[13:0] 0 D
n
[13:0]
40D
n+3
[13:0] 0 D
n+2
[13:0]
DLE
%HJLQQLQJRI-3(*VWUHDP
-3(*GDWD
'&0,B+6<1&
-3(*SDFNHWGDWD
'&0,B96<1&
3DGGLQJGDWD
DWWKHHQGRIWKH-3(*VWUHDP
3URJUDPPDEOH
-3(*SDFNHWVL]H
(QGRI-3(*VWUHDP
3DFNHWGLVSDWFKLQJGHSHQGVRQWKHLPDJHFRQWHQW
7KLVUHVXOWVLQDYDULDEOHEODQNLQJGXUDWLRQ
To Next Page
Loading...
Need help?
General
