ST STM32L4 5 Series - Figure 278. Counter Timing Diagram, Internal Clock Divided by N; Figure 279. Counter Timing Diagram, Update Event When ARPE=0 (Timx_Arr Not Preloaded)

General-purpose timers (TIM2/TIM3/TIM4/TIM5) RM0351
988/1830 DocID024597 Rev 5
Figure 278. Counter timing diagram, internal clock divided by N
Figure 279. Counter timing diagram, Update event when ARPE=0 (TIMx_ARR not
preloaded)
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