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RM0351 Chrom-Art Accelerator™ controller (DMA2D)
391
occurs, a CLUT access error interrupt is raised assuming CAEIE is set to ‘1’ in
DMA2D_CR.
• Manual loading
The application has to program the CLUT manually through the DMA2D AHB slave
port to which the local CLUT memory is mapped.The foreground CLUT is located at
address offset 0x0400 and the background CLUT at address offset 0x0800.
The CLUT format can be 24 or 32 bits. It is configured through the CCM bit of the
DMA2D_FGPFCCR register (foreground CLUT) or DMA2D_BGPFCCR register
(background CLUT) as shown in Table 51: Supported CLUT color mode.
The way the CLUT data are organized in the system memory is specified in Table 52: CLUT
data order in system memory.
12.3.6 DMA2D blender
The DMA2D blender blends the source pixels by pair to compute the resulting pixel.
The blending is performed according to the following equation:
No configuration register is required by the blender. The blender usage depends on the
DMA2D operating mode defined in MODE[1:0] field of the DMA2D_CR register.
Table 51. Supported CLUT color mode
CCM CLUT color mode
0 32-bit ARGB8888
124-bit RGB888
Table 52. CLUT data order in system memory
CLUT Color Mode @ + 3 @ + 2 @ + 1 @ + 0
ARGB8888 A
0
[7:0] R
0
[7:0] G
0
[7:0] B
0
[7:0]
RGB888
B
1
[7:0] R
0
[7:0] G
0
[7:0] B
0
[7:0]
G
2
[7:0] B
2
[7:0] R
1
[7:0] G
1
[7:0]
R
3
[7:0] G
3
[7:0] B
3
[7:0] R
2
[7:0]
C
OUT
=
with α
Mult
=
C
FG
.α
FG
+ C
BG
.α
BG
- C
BG
.α
Mult
α
OUT
255
α
FG
. α
BG
with C = R or G or B
α
OUT
= α
FG
+ α
BG
- α
Mult
Division is rounded to the nearest lower integer
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