DocID024597 Rev 5 449/1830
RM0351 Flexible static memory controller (FSMC)
471
Figure 55. Synchronous multiplexed write mode waveforms - PSRAM (CRAM)
1. The memory must issue NWAIT signal one cycle in advance, accordingly WAITCFG must be programmed
to 0.
2. Byte Lane (NBL) outputs are not shown, they are held low while NEx is active.
!DDR;= DATA
ADDR;=
-EMORYTRANSACTIONBURSTOFHALFWORDS
(#,+
#,+
!;=
.%X
./%
.7%
(I:
.!$6
.7!)4
7!)4#&'
!$;=
CLOCK CLOCK
$!4,!4
INSERTEDWAITSTATE
AIF
#,+CYCLES
DATA
Table 90. FMC_BCRx bit fields
Bit number Bit name Value to set
31-22 Reserved 0x000
21 WFDIS
As needed (this bit is reserved for STM32L475xx/476xx/486xx
devices)
20 CCLKEN As needed
19 CBURSTRW 0x1
18:16 CPSIZE As needed (0x1 for CRAM 1.5)
15 ASYNCWAIT 0x0
14 EXTMOD 0x0
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