DocID024597 Rev 5 167/1830
RM0351 Power control (PWR)
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Peripheral clock gating
In Run mode, the HCLK and PCLK for individual peripherals and memories can be stopped
at any time to reduce the power consumption.
To further reduce the power consumption in Sleep mode, the peripheral clocks can be
disabled prior to executing the WFI or WFE instructions.
The peripheral clock gating is controlled by the RCC_AHBxENR and RCC_APBxENR
registers.
Disabling the peripherals clocks in Sleep mode can be performed automatically by resetting
the corresponding bit in the RCC_AHBxSMENR and RCC_APBxSMENR registers.
5.3.2 Low-power run mode (LP run)
To further reduce the consumption when the system is in Run mode, the regulator can be
configured in low-power mode. In this mode, the system frequency should not exceed
2MHz.
Please refer to the product datasheet for more details on voltage regulator and peripherals
operating conditions.
I/O states in Low-power run mode
In Low-power run mode, all I/O pins keep the same state as in Run mode.
Entering the Low-power run mode
To enter the Low-power run mode, proceed as follows:
1. Optional: Jump into the SRAM and power-down the Flash by setting the RUN_PD bit in
the Flash access control register (FLASH_ACR).
2. Decrease the system clock frequency below 2 MHz.
3. Force the regulator in low-power mode by setting the LPR bit in the PWR_CR1 register.
Refer to Table 24: Low-power run on how to enter the Low-power run mode.
Exiting the Low-power run mode
To exit the Low-power run mode, proceed as follows:
1. Force the regulator in main mode by clearing the LPR bit in the PWR_CR1 register.
2. Wait until REGLPF bit is cleared in the PWR_SR2 register.
3. Increase the system clock frequency.
Refer to Table 24: Low-power run on how to exit the Low-power run mode.
Table 24. Low-power run
Low-power run mode Description
Mode entry
Decrease the system clock frequency below 2 MHz
LPR = 1
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