Voltage reference buffer (VREFBUF) RM0351
672/1830 DocID024597 Rev 5
21 Voltage reference buffer (VREFBUF)
21.1 Introduction
The STM32L4x5/STM32L4x6 devices embed a voltage reference buffer which can be used
as voltage reference for ADCs, DACs and also as voltage reference for external
components through the VREF+ pin. When the VREF+ pin is double-bonded with VDDA pin
in a package, the voltage reference buffer is not available and must be kept disable (refer to
datasheet for packages pinout description).
21.2 VREFBUF functional description
The internal voltage reference buffer supports two voltages, which are configured with VRS
bit in the VREFBUF_CSR register:
• V
REF_OUT1
around 2.048 V. This requires V
DDA
equal to or higher than 2.4 V.
• V
REF_OUT2
around 2.5 V. This requires V
DDA
equal to or higher than 2.8 V.
The internal voltage reference can be configured in four different modes depending on
ENVR and HIZ bits configuration. These modes are provided in the table below:
After enabling the VREFBUF buffer by setting ENVR bit and clearing HIZ bit in the
VREFBUF_CSR register, the user must wait until VRR bit is set, meaning that the voltage
reference output has reached its expected value.
21.3 VREFBUF registers
21.3.1 VREFBUF control and status register (VREFBUF_CSR)
Address offset: 0x00
Reset value: 0x0000 0002
Table 138. VREFBUF buffer modes
ENVR HIZ VREFBUF buffer configuration
00
VREFBUF buffer OFF:
– VREF+ pin pulled-down to V
SSA
.
01
External voltage reference mode (default value):
–VREFBUF buffer OFF
– VREF+ pin floating.
10
Internal voltage reference mode:
–VREFBUF buffer ON
– VREF+ pin connected to VREFBUF buffer output.
11
Hold mode:
–VREFBUF buffer OFF
– VREF+ pin floating. The voltage is held with the external capacitor
–V
RR
detection disabled and VRR bit keeps last state.
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