Embedded Flash memory (FLASH) RM0351
128/1830 DocID024597 Rev 5
3.7.8 Flash option register (FLASH_OPTR)
Address offset: 0x20
Reset value: 0xFXXX XXXX. Register bits are loaded with values from Flash memory at
OBL.
Access: no wait state when no Flash memory operation is on going, word, half-word and
byte access
Bit 31 ECCD: ECC detection
Set by hardware when two ECC errors have been detected. When this bit is set,
a NMI is generated
Cleared by writing 1.
Bit 30 ECCC: ECC correction
Set by hardware when one ECC error has been detected and corrected. An
interrupt is generated if ECCIE is set.
Cleared by writing 1.
Bits 29:25 Reserved, must be kept at reset value.
Bit 24 ECCIE: ECC correction interrupt enable
0: ECCC interrupt disabled
1: ECCC interrupt enabled.
Bits 23:21 Reserved, must be kept at reset value.
Bit 20 SYSF_ECC: System Flash ECC fail
This bit indicates that the ECC error correction or double ECC error detection is
located in the System Flash.
Bit 19 BK_ECC: ECC fail bank
This bit indicates which bank is concerned by the ECC error correction or by the
double ECC error detection.
0: bank 1
1: bank 2
Bits 18:0 ADDR_ECC: ECC fail address
This bit indicates which address in the bank is concerned by the ECC error
correction or by the double ECC error detection.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res.
n
BOOT0
nSW
BOOT0
SRAM2
_RST
SRAM2
_PE
nBOOT
1
Res.
DUAL
BANK
BFB2
WWDG
_SW
IWGD_
STDBY
IWDG_
StOP
IWDG_
SW
rw rw rw rw rw rw rw rw rw rw rw
1514131211109876543210
Res.
nRST_
SHDW
nRST_
STDBY
nRST_
STOP
Res. BOR_LEV[2:0] RDP[7:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw
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