Flexible static memory controller (FSMC) RM0351
432/1830 DocID024597 Rev 5
Mode 2/B - NOR Flash
Figure 42. Mode2 and mode B read access waveforms
Table 76. FMC_BWTRx bit fields
Bit number Bit name Value to set
31:30 Reserved 0x0
29:28 ACCMOD 0x0
27:24 DATLAT Don’t care
23:20 CLKDIV Don’t care
19:16 BUSTURN Time between NEx high to NEx low (BUSTURN HCLK).
15:8 DATAST
Duration of the second access phase (DATAST HCLK cycles) for write
accesses.
7:4 ADDHLD Don’t care
3:0 ADDSET
Duration of the first access phase (ADDSET HCLK cycles) for write
accesses.
Minimum value for ADDSET is 0.
069
$>@
12(
$''6(7 '$7$67
0HPRU\WUDQVDFWLRQ
1([
'>@
+&/.F\FOHV +&/.F\FOHV
1:(
1$'9
GDWDGULYHQ
E\PHPRU\
+LJK
To Next Page
Loading...
Need help?
General
