DocID024597 Rev 5 1191/1830
RM0351 Real-time clock (RTC)
1230
38.3.3 Clock and prescalers
The RTC clock source (RTCCLK) is selected through the clock controller among the LSE
clock, the LSI oscillator clock, and the HSE clock. For more information on the RTC clock
source configuration, refer to Section 6: Reset and clock control (RCC).
A programmable prescaler stage generates a 1 Hz clock which is used to update the
calendar. To minimize power consumption, the prescaler is split into 2 programmable
prescalers (see Figure 374: RTC block diagram):
• A 7-bit asynchronous prescaler configured through the PREDIV_A bits of the
RTC_PRER register.
• A 15-bit synchronous prescaler configured through the PREDIV_S bits of the
RTC_PRER register.
Note: When both prescalers are used, it is recommended to configure the asynchronous prescaler
to a high value to minimize consumption.
The asynchronous prescaler division factor is set to 128, and the synchronous division
factor to 256, to obtain an internal clock frequency of 1 Hz (ck_spre) with an LSE frequency
of 32.768 kHz.
The minimum division factor is 1 and the maximum division factor is 2
22
.
This corresponds to a maximum input frequency of around 4 MHz.
f
ck_apre
is given by the following formula:
The ck_apre clock is used to clock the binary RTC_SSR subseconds downcounter. When it
reaches 0, RTC_SSR is reloaded with the content of PREDIV_S.
f
ck_spre
is given by the following formula:
Table 211. RTC functions over modes
Pin RTC functions
Functional in all low-
power modes except
Standby/Shutdown
modes
Functional in
Standby/Shutdown
mode
Functional in
V
BAT
mode
PC13
RTC_TAMP1
RTC_TS
RTC_OUT
YES YES YES
PA0 RTC_TAMP2 YES YES YES
PE6 RTC_TAMP3 YES YES YES
PB2 RTC_OUT YES NO NO
PB15 RTC_REFIN YES NO NO
f
CK_APRE
f
RTCCLK
PREDIV_A 1+
---------------------------------------
=
f
CK_SPRE
f
RTCCLK
PREDIV_S 1+()PREDIV_A 1+()×
-----------------------------------------------------------------------------------------------
=
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