ST STM32L4 5 Series - Figure 218. Counter Timing Diagram, Update Event When ARPE=0 (Timx_Arr Not Preloaded); Figure 219. Counter Timing Diagram, Update Event When ARPE=1 (Timx_Arr Preloaded)

DocID024597 Rev 5 883/1830
RM0351 Advanced-control timers (TIM1/TIM8)
981
Figure 218. Counter timing diagram, update event when ARPE=0 (TIMx_ARR not
preloaded)
Figure 219. Counter timing diagram, update event when ARPE=1 (TIMx_ARR
preloaded)
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