Embedded Flash memory (FLASH) RM0351
120/1830 DocID024597 Rev 5
For example, to protect by WRP from the address 0x0806 2800 (included) to the address
0x0807 07FF (included):
• if boot in flash is done in Bank 1, FLASH_WRP1AR register must be programmed with:
– WRP1A_STRT = 0xC5.
– WRP1A_END = 0xE0.
WRP1B_STRT and WRP1B_END in FLASH_WRP1BR can be used instead (area “B”
in Bank 1).
• If the two banks are swapped, the protection must apply to bank 2, and
FLASH_WRP2AR register must be programmed with:
– WRP2A_STRT = 0xC5.
– WRP2A_END = 0xE0.
WRP2B_STRT and WRP2B_END in FLASH_WRP2BR can be used instead (area “B
in Bank 2).
When WRP is active, it cannot be erased or programmed. Consequently, a software mass
erase cannot be performed if one area is write-protected.
If an erase/program operation to a write-protected part of the Flash memory is attempted,
the write protection error flag (WRPERR) is set in the FLASH_SR register. This flag is also
set for any write access to:
– OTP area
– part of the Flash memory that can never be written like the ICP
– PCROP area.
Note: When the memory read protection level is selected (RDP level = 1), it is not possible to
program or erase Flash memory if the CPU debug features are connected (JTAG or single
wire) or boot code is being executed from RAM or System flash, even if WRP is not
activated.
Note: To validate the WRP options, the option bytes must be reloaded through the OBL_LAUNCH
bit in Flash control register.
3.6 FLASH interrupts
Table 16. Flash interrupt request
Interrupt event Event flag
Event flag/interrupt
clearing method
Interrupt enable control
bit
End of operation EOP
(1)
1. EOP is set only if EOPIE is set.
Write EOP=1 EOPIE
Operation error OPERR
(2)
2. OPERR is set only if ERRIE is set.
Write OPERR=1 ERRIE
Read error RDERR Write RDERR=1 RDERRIE
ECC correction ECCC Write ECCC=1 ECCCIE
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