Single Wire Protocol Master Interface (SWPMI) RM0351
1510/1830 DocID024597 Rev 5
44.6.2 SWPMI Bitrate register (SWPMI_BRR)
Address offset: 0x04
Reset value: 0x0000 0001
Bit 2 RXMODE: Reception buffering mode
This bit is used to choose the reception buffering mode. This bit is relevant only when
TXDMA bit is set (refer to Table 262: Buffer modes selection for transmission/reception).
0: SWPMI is configured in Single software buffer mode for reception
1: SWPMI is configured in Multi software buffer mode for reception.
Note: This bit cannot be written while SWPACT bit is set.
Bit 1 TXDMA: Transmission DMA enable
This bit is used to enable the DMA mode in transmission
0: DMA is disabled for transmission
1: DMA is enabled for transmission
Note: TXDMA is automatically cleared if the payload size of the transmitted frame is given as
0x00 (in the least significant byte of TDR for the first word of a frame). TXDMA is also
automatically cleared on underrun events (when TXUNRF flag is set in the SWP_ISR
register)
Bit 0 RXDMA: Reception DMA enable
This bit is used to enable the DMA mode in reception
0: DMA is disabled for reception
1: DMA is enabled for reception
Table 262. Buffer modes selection for transmission/reception
Buffer mode No software buffer Single software buffer Multi software buffer
RXMODE/TXMODE x 0 1
RXDMA/TXDMA 0 1 1
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
1514131211109876543210
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. BR[5:0]
rw rw rw rw rw rw
Bits 31:6 Reserved, must be kept at reset value
Bits 5:0 BR[5:0]: Bitrate prescaler
This field must be programmed to set SWP bus bitrate, taking into account the F
SWPCLK
programmed in the RCC (Reset and Clock Control), according to the following formula:
F
SWP
= F
SWPCLK
/ ((BR[5:0]+1)x4)
Note: The programmed bitrate must stay within the following range: from 100 kbit/s up to
2Mbit/s.
BR[5:0] cannot be written while SWPACT bit is set in the SWPMI_CR register.
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