ST STM32L4 5 Series - Figure 29. DMA Block Diagram

DocID024597 Rev 5 335/1830
RM0351 Direct memory access controller (DMA)
356
11.4 DMA functional description
The block diagram is shown in the following figure.
Figure 29. DMA block diagram
The DMA controller performs direct memory transfer by sharing the system bus with the
Cortex
®
-M4 core. The DMA request may stop the CPU access to the system bus for some
bus cycles, when the CPU and DMA are targeting the same destination (memory or
peripheral). The bus matrix implements round-robin scheduling, thus ensuring at least half
of the system bus bandwidth (both to memory and peripheral) for the CPU.
11.4.1 DMA transactions
After an event, the peripheral sends a request signal to the DMA Controller. The DMA
controller serves the request depending on the channel priorities. As soon as the DMA
Controller accesses the peripheral, an Acknowledge is sent to the peripheral by the DMA
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