ST STM32L4 5 Series User Manual

DocID024597 Rev 5 1811/1830
RM0351 Revision history
1823
50 Revision history
Table 327. Document revision history
Date Revision Changes
28-May-2015 1 Initial release.
15-Oct-2015 2
PWR
Updated Section 5.1: Power supplies.
Updated Section : Entering low power mode.
Updated Table 25: Sleep.
Updated Table 26: Low-power sleep.
Updated Table 27: Stop 0 mode.
Updated Table 29: Stop 2 mode.
Updated Table 30: Standby mode.
Updated Table 27: Stop 0 mode.
Renamed bit EIWF into EIWUL in Section 5.4.3: Power
control register 3 (PWR_CR3).
GPIO
Updated OSPEEDy[1:0] definition in Section 8.4.3:
GPIO port output speed register (GPIOx_OSPEEDR) (x
= A..I).
FMC
Updated Section : SRAM/NOR-Flash chip-select timing
registers 1..4 (FMC_BTR1..4).
Updated Section : SRAM/NOR-Flash write timing
registers 1..4 (FMC_BWTR1..4).
ADC
Updated Figure 69: ADC3 connectivity.
Updated Section 18.3.17: Stopping an ongoing
conversion (ADSTP, JADSTP).
Added formula in Bullet.
VREFBUF
Updated Table 138: VREFBUF buffer modes.
DFSDM
Updated clock range in Section : SPI data input format
operation and Section : Manchester coded data input
format operation.
LCD
Updated Section 25.2: LCD main features.
TSC
Updated Table 167: Spread spectrum deviation versus
AHB clock frequency.
Updated Table 169: Effect of low-power modes on TSC.
TIM2/TIM3/TIM4/TIM5
Updated Bullet in Section 31.3.13: One-pulse mode.

ST STM32L4 5 Series Specifications

General

Brand	ST
Model	STM32L4 5 Series
Category	Microcontrollers
Language	English