Chrom-Art Accelerator™ controller (DMA2D) RM0351
364/1830 DocID024597 Rev 5
12.3.7 DMA2D output PFC
The output PFC performs the pixel format conversion from 32 bits to the output format
defined in the CM[2:0] field of the DMA2D output pixel format converter configuration
register (DMA2D_OPFCCR).
The supported output formats are given in Table 53: Supported color mode in output
Note: To support the alternate format, the calculated alpha value can be inverted setting the AI bit
of the DMA2D_OPFCCR registers. This applies also to the Alpha value used in the
DMA2D_OCOLR.
The R and B fields can also be swapped setting the RBS bit of the DMA2D_OPFCCR
registers. This applies also to the RGB order used in the DMA2D_OCOLR.
12.3.8 DMA2D output FIFO
The output FIFO programs the pixels according to the color format defined in the output
PFC.
The destination area is defined through a set of control registers:
• DMA2D output memory address register (DMA2D_OMAR)
• DMA2D output offset register (DMA2D_OOR)
• DMA2D number of lines register (number of lines and pixel per lines) (DMA2D_NLR)
If the DMA2D operates in register-to-memory mode, the configured output rectangle is filled
by the color specified in the DMA2D output color register (DMA2D_OCOLR) which contains
a fixed 32-bit, 24-bit or 16-bit value. The format is selected by the CM[2:0] field of the
DMA2D_OPFCCR register.
The data are stored into the memory in the order defined in Table 54: Data order in memory
Table 53. Supported color mode in output
CM[2:0] Color mode
000 ARGB8888
001 RGB888
010 RGB565
011 ARGB1555
100 ARGB4444
Table 54. Data order in memory
Color Mode@ + 3@ + 2@ + 1@ + 0
ARGB8888 A
0
[7:0] R
0
[7:0] G
0
[7:0] B
0
[7:0]
RGB888
B
1
[7:0] R
0
[7:0] G
0
[7:0] B
0
[7:0]
G
2
[7:0] B
2
[7:0] R
1
[7:0] G
1
[7:0]
R
3
[7:0] G
3
[7:0] B
3
[7:0] R
2
[7:0]
RGB565 R
1
[4:0]G
1
[5:3] G
1
[2:0]B
1
[4:0] R
0
[4:0]G
0
[5:3] G
0
[2:0]B
0
[4:0]
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