ST STM32L4 5 Series - System and Memory Overview; System Architecture

System and memory overview RM0351
68/1830 DocID024597 Rev 5
2 System and memory overview
2.1 System architecture
The main system consists of 32-bit multilayer AHB bus matrix that interconnects:
• Up to six masters:
–Cortex
®
-M4 with FPU core I-bus
–Cortex
®
-M4 with FPU core D-bus
–Cortex
®
-M4 with FPU core S-bus
–DMA1
–DMA2
– DMA2D (only for STM32L496xx/4A6xx devices)
• Up to eight slaves:
– Internal Flash memory on the ICode bus
– Internal Flash memory on DCode bus
– Internal SRAM1 (96 KB for STM32L475xx/476xx/486xx devices, 256 KB for
STM32L496xx/4A6xx devices)
– Internal SRAM2 (32 KB for STM32L475xx/476xx/486xx devices, 64 KB for
STM32L496xx/4A6xx devices)
– AHB1 peripherals including AHB to APB bridges and APB peripherals (connected
to APB1 and APB2)
– AHB2 peripherals
– Flexible Memory Controller (FMC)
– Quad SPI memory interface (QUADSPI)
On STM32L475xx/476xx/486xx devices, FMC and QUADSPI slaves are merged into same
port.
The bus matrix provides access from a master to a slave, enabling concurrent access and
efficient operation even when several high-speed peripherals work simultaneously. This
architecture is shown in Figure 1 for STM32L475xx/476xx/486xx devices, and shown in
Figure 2 for STM32L496xx/4A6xx devices: