ST STM32L4 5 Series - Figure 493. SDMMC Adapter

SD/SDIO/MMC card host interface (SDMMC) RM0351
1522/1830 DocID024597 Rev 5
45.3.1 SDMMC adapter
Figure 493 shows a simplified block diagram of an SDMMC adapter.
Figure 493. SDMMC adapter
The SDMMC adapter is a multimedia/secure digital memory card bus master that provides
an interface to a multimedia card stack or to a secure digital memory card. It consists of five
subunits:
• Adapter register block
• Control unit
• Command path
• Data path
• Data FIFO
Note: The adapter registers and FIFO use the APB2 bus clock domain (PCLK2). The control unit,
command path and data path use the SDMMC adapter clock domain (SDMMCCLK).
Adapter register block
The adapter register block contains all system registers. This block also generates the
signals that clear the static flags in the multimedia card. The clear signals are generated
when 1 is written into the corresponding bit location in the SDMMC Clear register.
Control unit
The control unit contains the power management functions and the clock divider for the
memory card clock.
There are three power phases:
• power-off
• power-up
• power-on
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