ST STM32L4 5 Series User Manual

DocID024597 Rev 5 893/1830
RM0351 Advanced-control timers (TIM1/TIM8)
981
30.3.4 External trigger input
The timer features an external trigger input ETR. It can be used as:
• external clock (external clock mode 2, see Section 30.3.5)
• trigger for the slave mode (see Section 30.3.26)
• PWM reset input for cycle-by-cycle current regulation (see Section 30.3.7)
Figure 232 below describes the ETR input conditioning. The input polarity is defined with the
ETP bit in TIMxSMCR register. The trigger can be prescaled with the divider programmed
by the ETPS[1:0] bitfield and digitally filtered with the ETF[3:0] bitfield.
Figure 232. External trigger input block
The ETR input comes from multiple sources: input pins (default configuration), comparator
outputs and analog watchdogs. The selection is done with:
• the ETRSEL[2:0] bitfield in the TIMx_OR2 register
• the ETR_ADC1_RMP bitfield in the TIMxOR1[1:0] register
• the ETR_ADC3_RMP bitfield in the TIMxOR1[3:2] register.
Figure 233. TIM1 ETR input circuitry
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ST STM32L4 5 Series Specifications

General

Brand	ST
Model	STM32L4 5 Series
Category	Microcontrollers
Language	English