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DocID024597 Rev 5 185/1830

RM0351 Power control (PWR)

198

5.4.6 Power status register 2 (PWR_SR2)

Address offset: 0x14

Reset value: 0x0000 0000. This register is partially reset when exiting Standby/Shutdown

modes.

Bits 31:16 Reserved, must be kept at reset value.

Bit 15 WUFI: Wakeup flag internal

This bit is set when a wakeup is detected on the internal wakeup line. It is cleared when all

internal wakeup sources are cleared.

Bits 14:9 Reserved, must be kept at reset value.

Bit 8 SBF: Standby flag

This bit is set by hardware when the device enters the Standby mode and is cleared by

setting the CSBF bit in the PWR_SCR register, or by a power-on reset. It is not cleared by the

system reset.

0: The device did not enter the Standby mode

1: The device entered the Standby mode

Bits 7:5 Reserved, must be kept at reset value.

Bit 4 WUF5: Wakeup flag 5

This bit is set when a wakeup event is detected on wakeup pin, WKUP5. It is cleared by

writing ‘1’ in the CWUF5 bit of the PWR_SCR register.

Bit 3 WUF4: Wakeup flag 4

This bit is set when a wakeup event is detected on wakeup pin,WKUP4. It is cleared by

writing ‘1’ in the CWUF4 bit of the PWR_SCR register.

Bit 2 WUF3: Wakeup flag 3

This bit is set when a wakeup event is detected on wakeup pin, WKUP3. It is cleared by

writing ‘1’ in the CWUF3 bit of the PWR_SCR register.

Bit 1 WUF2: Wakeup flag 2

This bit is set when a wakeup event is detected on wakeup pin, WKUP2. It is cleared by

writing ‘1’ in the CWUF2 bit of the PWR_SCR register.

Bit 0 WUF1: Wakeup flag 1

This bit is set when a wakeup event is detected on wakeup pin, WKUP1. It is cleared by

writing ‘1’ in the CWUF1 bit of the PWR_SCR register.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

1514131211109876543210

PVMO4 PVMO3 PVMO2 PVMO1 PVDO VOSF

REGLP

Res. Res. Res. Res. Res. Res. Res. Res.

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ST STM32L4 5 Series User Manual

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