ST STM32L4 5 Series User Manual

DocID024597 Rev 5 127/1830
RM0351 Embedded Flash memory (FLASH)
136
3.7.7 Flash ECC register (FLASH_ECCR)
Address offset: 0x18
Reset value: 0x0000 0000
Access: no wait state when no Flash memory operation is on going, word, half-word and
byte access
Bit 15 MER2: Bank 2 Mass erase
This bit triggers the bank 2 mass erase (all bank 2 user pages) when set.
Bits 14:12 Reserved, must be kept at reset value.
Bit 11 BKER: Page number MSB (Bank selection)
0: Bank 1 is selected for page erase
1: Bank 2 is selected for page erase
Bits 10:3 PNB[7:0]: Page number selection
These bits select the page to erase:
If BKER = 0:
00000000: page 0
00000001: page 1
...
11111111: page 255
If BKER=1
00000000: page 256
00000001: page 257
...
11111111: page 511
Bit 2 MER1: Bank 1 Mass erase
This bit triggers the bank 1 mass erase (all bank 1 user pages) when set.
Bit 1 PER: Page erase
0: page erase disabled
1: page erase enabled
Bit 0 PG: Programming
0: Flash programming disabled
1: Flash programming enabled
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ECCD ECCC Res. Res. Res. Res. Res.
ECCC
IE
Res. Res. Res.
SYSF_
ECC
BK
_ECC
ADDR_ECC[18:16]
rc_w1 rc_w1 rw r r r r r
1514131211109 8 765432 1 0
ADDR_ECC[15:0]
rrrrrr r r rrrrrr r r

ST STM32L4 5 Series Specifications

General

Brand	ST
Model	STM32L4 5 Series
Category	Microcontrollers
Language	English