DocID024597 Rev 5 369/1830
RM0351 Chrom-Art Accelerator™ controller (DMA2D)
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When the last pixel of this line has been transferred, the TWIF flag of the DMA2D_ISR
register is raised and an interrupt is generated if the TWIE bit of the DMA2D_CR is set.
12.3.14 Error management
Two kind of errors can be triggered:
• AHB master port errors signaled by the TEIF flag of the DMA2D_ISR register.
• Conflicts caused by CLUT access (CPU trying to access the CLUT while a CLUT
loading or a DMA2D transfer is ongoing) signalled by the CAEIF flag of the
DMA2D_ISR register.
Both flags are associated to their own interrupt enable flag in the DMA2D_CR register to
generate an interrupt if need be (TEIE and CAEIE).
12.3.15 AHB dead time
To limit the AHB bandwidth usage, a dead time between two consecutive AHB accesses
can be programmed.
This feature can be enabled by setting the EN bit in the DMA2D_AMTCR register.
The dead time value is stored in the DT[7:0] field of the DMA2D_AMTCR register. This
value represents the guaranteed minimum number of cycles between two consecutive
transactions on the AHB bus.
The update of the dead time value while the DMA2D is running will be taken into account for
the next AHB transfer.
12.4 DMA2D interrupts
An interrupt can be generated on the following events:
• Configuration error
• CLUT transfer complete
• CLUT access error
• Transfer watermark reached
• Transfer complete
• Transfer error
Separate interrupt enable bits are available for flexibility.
Table 55. DMA2D interrupt requests
Interrupt event Event flag Enable control bit
Configuration error CEIF CEIE
CLUT transfer complete CTCIF CTCIE
CLUT access error CAEIF CAEIE
Transfer watermark TWF TWIE
Transfer complete TCIF TCIE
Transfer error TEIF TEIE
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