Chrom-Art Accelerator™ controller (DMA2D) RM0351
368/1830 DocID024597 Rev 5
The wrong configurations that can be detected are listed below:
• Foreground CLUT automatic loading: MA bits of DMA2D_FGCMAR are not aligned
with CCM of DMA2D_FGPFCCR.
• Background CLUT automatic loading: MA bits of DMA2D_BGCMAR are not aligned
with CCM of DMA2D_BGPFCCR
• Memory transfer (except in register-to-memory mode): MA bits of DMA2D_FGMAR are
not aligned with CM of DMA2D_FGPFCCR
• Memory transfer (except in register-to-memory mode): CM bits of DMA2D_FGPFCCR
are invalid
• Memory transfer (except in register-to-memory mode): PL bits of DMA2D_NLR are odd
while CM of DMA2D_FGPFCCR is A4 or L4
• Memory transfer (except in register-to-memory mode): LO bits of DMA2D_FGOR are
odd while CM of DMA2D_FGPFCCR is A4 or L4
• Memory transfer (only in blending mode): MA bits of DMA2D_BGMAR are not aligned
with the CM of DMA2D_BGPFCCR
• Memory transfer: (only in blending mode) CM bits of DMA2D_BGPFCCR are invalid
• Memory transfer (only in blending mode): PL bits of DMA2D_NLR odd while CM of
DMA2D_BGPFCCR is A4 or L4
• Memory transfer (only in blending mode): LO bits of DMA2D_BGOR are odd while CM
of DMA2D_BGPFCCR is A4 or L4
• Memory transfer (except in memory to memory mode): MA bits of DMA2D_OMAR are
not aligned with CM bits of DMA2D_OPFCCR.
• Memory transfer (except in memory to memory mode): CM bits of DMA2D_OPFCCR
are invalid
• Memory transfer: NL bits of DMA2D_NLR = 0
• Memory transfer: PL bits of DMA2D_NLR = 0
12.3.12 DMA2D transfer control (start, suspend, abort and completion)
Once the DMA2D is configured, the transfer can be launched by setting the START bit of the
DMA2D_CR register. Once the transfer is completed, the START bit is automatically reset
and the TCIF flag of the DMA2D_ISR register is raised. An interrupt can be generated if the
TCIE bit of the DMA2D_CR is set.
The user application can suspend the DMA2D at any time by setting the SUSP bit of the
DMA2D_CR register. The transaction can then be aborted by setting the ABORT bit of the
DMA2D_CR register or can be restarted by resetting the SUSP bit of the DMA2D_CR
register.
The user application can abort at any time an ongoing transaction by setting the ABORT bit
of the DMA2D_CR register. In this case, the TCIF flag is not raised.
Automatic CLUT transfers can also be aborted or suspended by using the ABORT or the
SUSP bit of the DMA2D_CR register.
12.3.13 Watermark
A watermark can be programmed to generate an interrupt when the last pixel of a given line
has been written to the destination memory area.
The line number is defined in the LW[15:0] field of the DMA2D_LWR register.
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