ST STM32L4 5 Series - Figure 289. Counter Timing Diagram, Internal Clock Divided by N; Figure 290. Counter Timing Diagram, Update Event with ARPE=1 (Counter Underflow)

DocID024597 Rev 5 995/1830
RM0351 General-purpose timers (TIM2/TIM3/TIM4/TIM5)
1052
Figure 289. Counter timing diagram, internal clock divided by N
Figure 290. Counter timing diagram, Update event with ARPE=1 (counter underflow)

)

069
&.B36&
7LPHUFORFN &.B&17
&RXQWHUUHJLVWHU
8SGDWHHYHQW8(9
&RXQWHUXQGHUIORZ
8SGDWHLQWHUUXSWIODJ
8,)

)' 
069
&.B36&
7LPHUFORFN &.B&17
&RXQWHUUHJLVWHU
8SGDWHHYHQW8(9
&RXQWHUXQGHUIORZ
8SGDWHLQWHUUXSWIODJ
8,)
      
&(1
$XWRUHORDGSUHORDG
UHJLVWHU
:ULWHDQHZYDOXHLQ7,0[B$55
     
)' 
$XWRUHORDGDFWLYH
UHJLVWHU