ST STM32L4 5 Series - Case 1: Master Interrupted First; Case 2: Slave Interrupted First; Figure 128. Interleaved Single Channel CH0 with Injected Sequence CH11, CH12; Figure 129. Two Interleaved Channels (CH1, CH2) with Injected Sequence CH11, CH12

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Figure 128. Interleaved single channel CH0 with injected sequence CH11, CH12
Figure 129. Two Interleaved channels (CH1, CH2) with injected sequence CH11, CH12
- case 1: Master interrupted first
Figure 130. Two Interleaved channels (CH1, CH2) with injected sequence CH11, CH12
- case 2: Slave interrupted first
DMA requests in dual ADC mode
In all dual ADC modes, it is possible to use two DMA channels (one for the master, one for
the slave) to transfer the data, like in single mode (refer to Figure 131: DMA Requests in
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