Digital-to-analog converter (DAC) RM0351
622/1830 DocID024597 Rev 5
maximum amplitude defined by the MAMPx[3:0] bits. Once the configured amplitude is
reached, the counter is decremented down to 0, then incremented again and so on.
It is possible to reset triangle wave generation by resetting the WAVEx[1:0] bits.
Figure 143. DAC triangle wave generation
Figure 144. DAC conversion (SW trigger enabled) with triangle wave generation
Note: 1 The DAC trigger must be enabled for noise generation by setting the TENx bit in the
DAC_CR register.
2 The MAMPx[3:0] bits must be configured before enabling the DAC, otherwise they cannot
be changed.
19.3.10 DAC channel modes
Each DAC channel can be configured in normal mode or sample and hold mode. The output
buffer can be enabled to allow a high drive capability. Before enabling output buffer, the
voltage offset needs to be calibrated. This calibration is performed at the factory (loaded
after reset) and can be adjusted by software during application operation.
Normal mode
In normal mode, there are four combinations, by changing the buffer state and by changing
the DAC_OUTx pin interconnections.
To enable the output buffer, the MODEx[2:0] bits in DAC_MCR register should be:
• 000: DAC is connected to the external pin
• 001: DAC is connected to external pin and to on-chip peripherals
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