DocID024597 Rev 5 1383/1830
RM0351 Low-power universal asynchronous receiver transmitter (LPUART)
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41.4.5 Tolerance of the LPUART receiver to clock deviation
The asynchronous receiver of the LPUART works correctly only if the total clock system
deviation is less than the tolerance of the LPUART receiver. The causes which contribute to
the total deviation are:
• DTRA: Deviation due to the transmitter error (which also includes the deviation of the
transmitter’s local oscillator)
• DQUANT: Error due to the baud rate quantization of the receiver
• DREC: Deviation of the receiver’s local oscillator
• DTCL: Deviation due to the transmission line (generally due to the transceivers which
can introduce an asymmetry between the low-to-high transition timing and the high-to-
low transition timing)
where
DWU is the error due to sampling point deviation when the wakeup from Stop mode is
used.
when M[1:0] = 01:
when M[1:0] = 00:
when M[1:0] = 10:
t
WULPUART
is the time between detecting the wakeup event and both clock (requested
by the peripheral) and regulator ready.
The LPUART receiver can receive data correctly at up to the maximum tolerated deviation
specified in Table 243:
• 7, 8 or 9-bit character length defined by the M bits in the LPUARTx_CR1 register
• 1 or 2 stop bits
DTRA DQUANT DREC DTCL DWU++++LPUART receiver tolerance<
DWU
t
WULPUART
11 Tbit×
------------------------------
=
DWU
t
WULPUART
10 Tbit×
------------------------------
=
DWU
t
WULPUART
9Tbit×
------------------------------
=
Table 243. Tolerance of the LPUART receiver
M bits 768 BRR <1024 1024 BRR < 2048 2048 BRR < 4096 4096 BRR
8 bits (M=00), 1 stop bit 1.82% 2.56% 3.90% 4.42%
9 bits (M=01), 1 stop bit 1.69% 2.33% 2.53% 4.14%
7 bits (M=10), 1 stop bit 2.08% 2.86% 4.35% 4.42%
8 bits (M=00), 2 stop bit 2.08% 2.86% 4.35% 4.42%
9 bits (M=01), 2 stop bit 1.82% 2.56% 3.90% 4.42%
7 bits (M=10), 2stop bit 2.34% 3.23% 4.92% 4.42%
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