DocID024597 Rev 5 1431/1830
RM0351 Serial peripheral interface (SPI)
1446
Figure 456. Master full-duplex communication in packed mode
Assumptions for master full-duplex communication in packed mode example:
• Data size = 5 bit
• Read/write FIFO is performed mostly by 16-bit access
• FRXTH=0
If DMA is used:
• Number of Tx frames to be transacted by DMA is set to 3
• Number of Rx frames to be transacted by DMA is set to 3
• PSIZE for both Tx and Rx DMA channel is set to 16-bit
• LDMA_TX=1 and LDMA_RX=1
See also : Communication diagrams on page 1427 for details about common assumptions
and notes.
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