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DocID024597 Rev 5
839/1830
RM0351
Advanced encryption stan
dard hardware accelerator (
AES)
852
28.13 AES
interrupt
s
T
able 17
8. AES interrupt
requests
Interrupt event
Event flag
Enable
control bit
Exit from
Wa
i
t
AES computation completed flag
CCF
CCFIE
yes
AES read error flag
RDERR
ERRIE
yes
AES write error flag
WRERR
ERRIE
yes
838
840
Table of Contents
Table of Contents
2
List of Tables
49
Documentation Conventions
67
Glossary
67
List of Abbreviations for Registers
67
Peripheral Availability
67
System and Memory Overview
68
System Architecture
68
Figure 1. System Architecture for Stm32L475Xx/476Xx/486Xx Devices
69
Figure 2. System Architecture for Stm32L496Xx/4A6Xx Devices
70
S0: I-Bus
70
S1: D-Bus
70
S2: S-Bus
70
Busmatrix
71
S3, S4: DMA-Bus
71
S5: DMA2D-Bus
71
Introduction
72
Memory Organization
72
Figure 3. Memory Map for Stm32L475Xx/476Xx/486Xx Devices
73
Figure 4. Memory Map for Stm32L496Xx/4A6Xx Devices
74
Addresses
75
Memory Map and Register Boundary Addresses
75
Table 1. Stm32L475Xx/476Xx/486Xx Devices Memory Map and Peripheral Register Boundary
75
Addresses
80
Table 2. Stm32L496Xx/4A6Xx Devices Memory Map and Peripheral Register Boundary
80
Bit Banding
83
Embedded SRAM
84
SRAM2 Parity Check
84
SRAM2 Write Protection
85
Table 3. SRAM2 Organization
85
Flash Memory Overview
87
SRAM2 Erase
87
SRAM2 Read Protection
87
Boot Configuration
88
Boot Configuration for Stm32L475Xx/476Xx/486Xx Devices
88
Table 4. Boot Modes
88
Table 5. Memory Mapping Versus Boot Mode/Physical Remap
89
Boot Configuration for Stm32L496Xx/4A6Xx Devices
90
Table 6. Boot Modes
90
Table 7. Memory Mapping Versus Boot Mode/Physical Remap
91
Embedded Flash Memory (FLASH)
93
FLASH Functional Description
93
FLASH Main Features
93
Flash Memory Organization
93
Introduction
93
Table 8. Flash Module - 1 MB Dual Bank Organization
94
Table 9. Flash Module - 512 KB Dual Bank Organization
95
Error Code Correction (ECC)
96
Table 10. Flash Module - 256 KB Dual Bank Organization
96
Read Access Latency
97
Table 11. Number of Wait States According to CPU Clock (HCLK) Frequency
97
Adaptive Real-Time Memory Accelerator (ART Accelerator™)
98
Figure 5. Sequential 16-Bit Instructions Execution
99
Flash Program and Erase Operations
100
Flash Main Memory Erase Sequences
101
Flash Main Memory Programming Sequences
102
Read-While-Write (RWW)
105
FLASH Option Bytes
107
Option Bytes Description
107
Table 12. Option Byte Format
107
Table 13. Option Byte Organization
107
Option Bytes Programming
113
FLASH Memory Protection
115
Read Protection (RDP)
115
Table 14. Flash Memory Read Protection Status
115
Figure 6. Changing the Read Protection (RDP) Level
117
Table 15. Access Status Versus Protection Level and Execution Modes
117
Proprietary Code Readout Protection (PCROP)
118
Write Protection (WRP)
119
FLASH Interrupts
120
Table 16. Flash Interrupt Request
120
Flash Access Control Register (FLASH_ACR)
121
FLASH Registers
121
Flash Power-Down Key Register (FLASH_PDKEYR)
122
Flash Key Register (FLASH_KEYR)
123
Flash Option Key Register (FLASH_OPTKEYR)
123
Flash Status Register (FLASH_SR)
124
Flash Control Register (FLASH_CR)
125
Flash ECC Register (FLASH_ECCR)
127
Flash Option Register (FLASH_OPTR)
128
Flash Bank 1 PCROP Start Address Register (FLASH_PCROP1SR)
130
Flash Bank 1 PCROP End Address Register (FLASH_PCROP1ER)
131
Flash Bank 1 WRP Area a Address Register (FLASH_WRP1AR)
131
Flash Bank 1 WRP Area B Address Register (FLASH_WRP1BR)
132
Flash Bank 2 PCROP Start Address Register (FLASH_PCROP2SR)
132
Flash Bank 2 PCROP End Address Register (FLASH_PCROP2ER)
133
Flash Bank 2 WRP Area a Address Register (FLASH_WRP2AR)
133
Flash Bank 2 WRP Area B Address Register (FLASH_WRP2BR)
134
FLASH Register Map
135
Table 17. Flash Interface - Register Map and Reset Values
135
Firewall (FW)
137
Firewall Main Features
137
Introduction
137
Figure 7. Stm32L4X5/Stm32L4X6 Firewall Connection Schematics
138
Firewall AMBA Bus Snoop
138
Firewall Functional Description
138
Functional Requirements
138
Firewall Segments
139
Segment Accesses and Properties
140
Table 18. Segment Accesses According to the Firewall State
140
Firewall Initialization
141
Table 19. Segment Granularity and Area Ranges
141
Figure 8. Firewall Functional States
142
Firewall States
142
Code Segment Length (FW_CSL)
144
Code Segment Start Address (FW_CSSA)
144
Firewall Registers
144
Non-Volatile Data Segment Length (FW_NVDSL)
145
Non-Volatile Data Segment Start Address (FW_NVDSSA)
145
Volatile Data Segment Length (FW_VDSL)
146
Volatile Data Segment Start Address (FW_VDSSA)
146
Configuration Register (FW_CR)
147
Firewall Register Map
149
Table 20. Firewall Register Map and Reset Values
149
Power Control (PWR)
150
Power Supplies
150
Figure 9. Power Supply Overview
151
Independent Analog Peripherals Supply
151
Independent I/O Supply Rail
152
Independent USB Transceivers Supply
152
Battery Backup Domain
153
Independent LCD Supply
153
Voltage Regulator
154
Figure 10. Internal Main Regulator Overview
155
VDD12 Domain
155
Dynamic Voltage Scaling Management
156
(Bor)
158
Figure 11. Brown-Out Reset Waveform
158
Power Supply Supervisor
158
Power-On Reset (POR) / Power-Down Reset (PDR) / Brown-Out Reset
158
Programmable Voltage Detector (PVD)
158
Figure 12. PVD Thresholds
159
Peripheral Voltage Monitoring (PVM)
159
Table 21. PVM Features
159
Low-Power Modes
160
Figure 13. Low-Power Modes Possible Transitions
162
Table 22. Low-Power Mode Summary
163
Table 23. Functionalities Depending on the Working Mode
164
Run Mode
166
Low-Power Run Mode (LP Run)
167
Table 24. Low-Power Run
167
Low Power Modes
168
Low-Power Sleep Mode (LP Sleep)
169
Sleep Mode
169
Table 25. Sleep
169
Stop 0 Mode
170
Table 26. Low-Power Sleep
170
Stop 1 Mode
172
Table 27. Stop 0 Mode
172
Stop 2 Mode
173
Table 28. Stop 1 Mode
173
Standby Mode
175
Table 29. Stop 2 Mode
175
Table 30. Standby Mode
177
Shutdown Mode
178
Auto-Wakeup from Low-Power Mode
179
Table 31. Shutdown Mode
179
Power Control Register 1 (PWR_CR1)
180
PWR Registers
180
Power Control Register 2 (PWR_CR2)
181
Power Control Register 3 (PWR_CR3)
182
Power Control Register 4 (PWR_CR4)
183
Power Status Register 1 (PWR_SR1)
184
Power Status Register 2 (PWR_SR2)
185
Power Status Clear Register (PWR_SCR)
186
Power Port a Pull-Up Control Register (PWR_PUCRA)
187
Power Port a Pull-Down Control Register (PWR_PDCRA)
188
Power Port B Pull-Up Control Register (PWR_PUCRB)
188
Power Port B Pull-Down Control Register (PWR_PDCRB)
189
Power Port C Pull-Up Control Register (PWR_PUCRC)
189
Power Port C Pull-Down Control Register (PWR_PDCRC)
190
Power Port D Pull-Up Control Register (PWR_PUCRD)
190
Power Port D Pull-Down Control Register (PWR_PDCRD)
191
Power Port E Pull-Up Control Register (PWR_PUCRE)
191
Power Port E Pull-Down Control Register (PWR_PDCRE)
192
Power Port F Pull-Up Control Register (PWR_PUCRF)
192
Power Port F Pull-Down Control Register (PWR_PDCRF)
193
Power Port G Pull-Up Control Register (PWR_PUCRG)
193
Power Port G Pull-Down Control Register (PWR_PDCRG)
194
Power Port H Pull-Up Control Register (PWR_PUCRH)
194
Power Port H Pull-Down Control Register (PWR_PDCRH)
195
Power Port I Pull-Up Control Register (PWR_PUCRI)
195
Power Port I Pull-Down Control Register (PWR_PDCRI)
196
PWR Register Map and Reset Value Table
197
Table 32. PWR Register Map and Reset Values
197
Reset
199
Reset and Clock Control (RCC)
199
Figure 14. Simplified Diagram of the Reset Circuit
200
Figure 15. Clock Tree (for Stm32L475Xx/476Xx/486Xx Devices)
204
Figure 16. Clock Tree (for Stm32L496Xx/4A6Xx Devices)
206
Figure 17. HSE/ LSE Clock Sources
207
Table 33. Clock Source Frequency
212
Figure 18. Frequency Measurement with TIM15 in Capture Mode
215
Figure 19. Frequency Measurement with TIM16 in Capture Mode
216
Figure 20. Frequency Measurement with TIM17 in Capture Mode
216
Table 34. RCC Register Map and Reset Values
274
Figure 21. CRS Block Diagram
280
Figure 22. CRS Counter Behavior
281
Table 35. Effect of Low-Power Modes on CRS
283
Table 36. Interrupt Control Bits
283
Table 37. CRS Register Map and Reset Values
289
Figure 23. Basic Structure of an I/O Port Bit
291
Figure 24. Basic Structure of a Five-Volt Tolerant I/O Port Bit
291
Table 38. Port Bit Configuration Table
292
Figure 25. Input Floating/Pull Up/Pull down Configurations
296
Figure 26. Output Configuration
297
Figure 27. Alternate Function Configuration
298
Figure 28. High Impedance-Analog Configuration
298
Table 39. GPIO Register Map and Reset Values
307
Table 40. SYSCFG Register Map and Reset Values
322
Table 41. Stm32L4X5/Stm32L4X6 Peripherals Interconnect Matrix
325
Table 42. DMA Implementation
334
Figure 29. DMA Block Diagram
335
Table 43. Programmable Data Width & Endian Behavior (When Bits PINC = MINC = 1)
338
Table 44. DMA Interrupt Requests
339
Figure 30. DMA1 Request Mapping
341
Figure 31. DMA2 Request Mapping
342
Table 45. Summary of the DMA1 Requests for each Channel
342
Table 46. Summary of the DMA2 Requests for each Channel
343
Table 47. DMA Register Map and Reset Values
354
Table 48. Supported Color Mode in Input
360
Table 49. Data Order in Memory
361
Table 51. Supported CLUT Color Mode
363
Table 52. CLUT Data Order in System Memory
363
Table 53. Supported Color Mode in Output
364
Table 54. Data Order in Memory
364
Table 55. DMA2D Interrupt Requests
369
Table 56. DMA2D Register Map and Reset Values
390
Table 57. Stm32L4X5/Stm32L4X6 Vector Table
393
Figure 33. Configurable Interrupt/Event Block Diagram
398
Figure 34. External Interrupt/Event GPIO Mapping
400
Table 58. EXTI Lines Connections
400
Table 59. Extended Interrupt/Event Controller Register Map and Reset Values
409
Figure 35. CRC Calculation Unit Block Diagram
411
Table 60. CRC Internal Input/Output Signals
411
Table 61. CRC Register Map and Reset Values
415
Figure 36. FMC Block Diagram
417
Figure 37. FMC Memory Banks
420
Table 62. NOR/PSRAM Bank Selection
420
Table 63. NOR/PSRAM External Memory Address
420
Table 64. NAND Memory Mapping and Timing Registers
421
Table 65. NAND Bank Selection
421
Table 66. Programmable NOR/PSRAM Access Parameters
423
Table 67. Non-Multiplexed I/O nor Flash Memory
423
Table 68. 16-Bit Multiplexed I/O nor Flash Memory
424
Table 69. Non-Multiplexed I/Os PSRAM/SRAM
424
Table 70. 16-Bit Multiplexed I/O PSRAM
424
Table 71. nor Flash/Psram: Example of Supported Memories and Transactions
425
Figure 38. Mode1 Read Access Waveforms
427
Figure 39. Mode1 Write Access Waveforms
428
Table 72. Fmc_Bcrx Bit Fields
428
Table 73. Fmc_Btrx Bit Fields
429
Figure 40. Modea Read Access Waveforms
430
Figure 41. Modea Write Access Waveforms
430
Table 74. Fmc_Bcrx Bit Fields
431
Table 75. Fmc_Btrx Bit Fields
431
Figure 42. Mode2 and Mode B Read Access Waveforms
432
Table 76. Fmc_Bwtrx Bit Fields
432
Figure 43. Mode2 Write Access Waveforms
433
Figure 44. Modeb Write Access Waveforms
433
Table 77. Fmc_Bcrx Bit Fields
434
Table 78. Fmc_Btrx Bit Fields
434
Figure 45. Modec Read Access Waveforms
435
Table 79. Fmc_Bwtrx Bit Fields
435
Figure 46. Modec Write Access Waveforms
436
Table 80. Fmc_Bcrx Bit Fields
436
Table 81. Fmc_Btrx Bit Fields
437
Table 82. Fmc_Bwtrx Bit Fields
437
Figure 47. Moded Read Access Waveforms
438
Figure 48. Moded Write Access Waveforms
438
Table 83. Fmc_Bcrx Bit Fields
439
Table 84. Fmc_Btrx Bit Fields
439
Figure 49. Muxed Read Access Waveforms
440
Table 85. Fmc_Bwtrx Bit Fields
440
Figure 50. Muxed Write Access Waveforms
441
Table 86. Fmc_Bcrx Bit Fields
441
Table 87. Fmc_Btrx Bit Fields
442
Figure 51. Asynchronous Wait During a Read Access Waveforms
443
Figure 52. Asynchronous Wait During a Write Access Waveforms
444
Figure 53. Wait Configuration Waveforms
446
Figure 54. Synchronous Multiplexed Read Mode Waveforms - NOR, PSRAM (CRAM)
447
Table 88. Fmc_Bcrx Bit Fields
447
Table 89. Fmc_Btrx Bit Fields
448
Figure 55. Synchronous Multiplexed Write Mode Waveforms - PSRAM (CRAM)
449
Table 90. Fmc_Bcrx Bit Fields
449
Table 91. Fmc_Btrx Bit Fields
450
Table 92. Programmable NAND Flash Access Parameters
458
Table 93. 8-Bit NAND Flash
458
Table 94. 16-Bit NAND Flash
459
Table 95. Supported Memories and Transactions
460
Figure 56. NAND Flash Controller Waveforms for Common Memory Access
461
Figure 57. Access to Non 'CE Don't Care' NAND-Flash
462
Table 96. ECC Result Relevant Bits
469
Table 97. FMC Register Map
470
Table 98. QUADSPI Implementation
472
Figure 58. QUADSPI Block Diagram When Dual-Flash Mode Is Disabled
473
Figure 59. QUADSPI Block Diagram When Dual-Flash Mode Is Enabled
473
Table 99. QUADSPI Pins
473
Figure 60. an Example of a Read Command in Quad Mode
474
Figure 61. an Example of a DDR Command in Quad Mode
478
Figure 62. Ncs When CKMODE = 0 (T = CLK Period)
486
Figure 63. Ncs When CKMODE = 1 in SDR Mode (T = CLK Period)
486
Figure 64. Ncs When CKMODE = 1 in DDR Mode (T = CLK Period)
486
Figure 65. Ncs When CKMODE = 1 with an Abort (T = CLK Period)
487
Table 100. QUADSPI Interrupt Requests
487
Table 101. QUADSPI Register Map and Reset Values
500
Table 102. Main ADC Features
503
Figure 66. ADC Block Diagram
504
Table 103. ADC Internal Signals
505
Table 104. ADC Pins
505
Figure 68. ADC1 Connectivity
508
Figure 69. ADC2 Connectivity
509
Figure 70. ADC3 Connectivity
510
Figure 71. ADC Calibration
513
Figure 72. Updating the ADC Calibration Factor
514
Figure 73. Mixing Single-Ended and Differential Channels
515
Figure 74. Enabling / Disabling the ADC
516
Figure 75. Analog to Digital Conversion Time
521
Figure 76. Stopping Ongoing Regular Conversions
522
Figure 77. Stopping Ongoing Regular and Injected Conversions
522
Table 105. Configuring the Trigger Polarity for Regular External Triggers
523
Table 106. Configuring the Trigger Polarity for Injected External Triggers
523
Figure 78. Triggers Are Shared between ADC Master and ADC Slave
524
Table 107. ADC1, ADC2 and ADC3 - External Triggers for Regular Channels
524
Table 108. ADC1, ADC2 and ADC3 - External Trigger for Injected Channels
525
Figure 79. Injected Conversion Latency
527
Figure 80. Example of JSQR Queue of Context (Sequence Change)
530
Figure 81. Example of JSQR Queue of Context (Trigger Change)
530
Figure 82. Example of JSQR Queue of Context with Overflow before Conversion
531
Figure 83. Example of JSQR Queue of Context with Overflow During Conversion
531
Figure 84. Example of JSQR Queue of Context with Empty Queue (Case JQM=0)
532
Figure 85. Example of JSQR Queue of Context with Empty Queue (Case JQM=1)
533
Figure 86. Flushing JSQR Queue of Context by Setting JADSTP=1 (JQM=0). Case When JADSTP Occurs During an Ongoing Conversion
533
Figure 87. Flushing JSQR Queue of Context by Setting JADSTP=1 (JQM=0). Case When JADSTP Occurs During an Ongoing Conversion and a New
534
Figure 88. Flushing JSQR Queue of Context by Setting JADSTP=1 (JQM=0). Case When JADSTP Occurs Outside an Ongoing Conversion
534
Trigger Occurs
534
Figure 89. Flushing JSQR Queue of Context by Setting JADSTP=1 (JQM=1)
535
Figure 90. Flushing JSQR Queue of Context by Setting ADDIS=1 (JQM=0)
535
Figure 91. Flushing JSQR Queue of Context by Setting ADDIS=1 (JQM=1)
536
Table 109. TSAR Timings Depending on Resolution
537
Figure 92. Single Conversions of a Sequence, Software Trigger
538
Figure 93. Continuous Conversion of a Sequence, Software Trigger
538
Figure 94. Single Conversions of a Sequence, Hardware Trigger
539
Figure 95. Continuous Conversions of a Sequence, Hardware Trigger
539
Table 110. Offset Computation Versus Data Resolution
540
Figure 96. Right Alignment (Offset Disabled, Unsigned Value)
541
Figure 97. Right Alignment (Offset Enabled, Signed Value)
541
Figure 98. Left Alignment (Offset Disabled, Unsigned Value)
542
Figure 99. Left Alignment (Offset Enabled, Signed Value)
542
Figure 100. Example of Overrun (OVR)
543
(Discen=0; Jdiscen=0)
547
Figure 101. AUTODLY=1, Regular Conversion in Continuous Mode, Software Trigger
547
Figure 102. AUTODLY=1, Regular HW Conversions Interrupted by Injected Conversions
547
(Discen=1, Jdiscen=1)
548
Figure 104. AUTODLY=1, Regular Continuous Conversions Interrupted by Injected Conversions
549
Figure 105. AUTODLY=1 in Auto- Injected Mode (JAUTO=1)
549
Figure 106. Analog Watchdog's Guarded Area
550
Table 111. Analog Watchdog Channel Selection
550
Table 112. Analog Watchdog 1 Comparison
551
Table 113. Analog Watchdog 2 and 3 Comparison
551
Figure 107. Adcy_Awdx_Out Signal Generation (on All Regular Channels)
552
Figure 108. Adcy_Awdx_Out Signal Generation (Awdx Flag Not Cleared by Software)
553
Figure 109. Adcy_Awdx_Out Signal Generation (on a Single Regular Channel)
553
Figure 110. Adcy_Awdx_Out Signal Generation (on All Injected Channels)
553
Figure 111. 20-Bit to 16-Bit Result Truncation
554
Figure 112. Numerical Example with 5-Bits Shift and Rounding
554
Table 114. Maximum Output Results Versus N and M (Gray Cells Indicate Truncation)
555
Figure 113. Triggered Regular Oversampling Mode (TROVS Bit = 1)
556
Figure 114. Regular Oversampling Modes (4X Ratio)
557
Figure 115. Regular and Injected Oversampling Modes Used Simultaneously
558
Figure 116. Triggered Regular Oversampling with Injection
558
Figure 117. Oversampling in Auto-Injected Mode
559
Table 115. Oversampler Operating Modes Summary
559
Figure 118. Dual ADC Block Diagram (1)
561
Figure 119. Injected Simultaneous Mode on 4 Channels: Dual ADC Mode
562
Figure 120. Regular Simultaneous Mode on 16 Channels: Dual ADC Mode
564
Figure 121. Interleaved Mode on 1 Channel in Continuous Conversion Mode: Dual ADC Mode
566
Figure 122. Interleaved Mode on 1 Channel in Single Conversion Mode: Dual ADC Mode
566
Figure 123. Interleaved Conversion with Injection
567
Figure 124. Alternate Trigger: Injected Group of each ADC
568
Figure 125. Alternate Trigger: 4 Injected Channels (each ADC) in Discontinuous Mode
569
Figure 126. Alternate + Regular Simultaneous
570
Figure 127. Case of Trigger Occurring During Injected Conversion
570
Case 1: Master Interrupted First
571
Case 2: Slave Interrupted First
571
Figure 128. Interleaved Single Channel CH0 with Injected Sequence CH11, CH12
571
Figure 129. Two Interleaved Channels (CH1, CH2) with Injected Sequence CH11, CH12
571
Figure 130. Two Interleaved Channels (CH1, CH2) with Injected Sequence CH11, CH12
571
Figure 131. DMA Requests in Regular Simultaneous Mode When Mdma=0B00
572
Figure 132. DMA Requests in Regular Simultaneous Mode When Mdma=0B10
573
Figure 133. DMA Requests in Interleaved Mode When Mdma=0B10
573
Figure 134. Temperature Sensor Channel Block Diagram
576
Figure 135. VBAT Channel Block Diagram
577
Figure 136. VREFINT Channel Block Diagram
577
Table 116. ADC Interrupts Per each ADC
579
Table 117. DELAY Bits Versus ADC Resolution
610
Table 118. ADC Global Register Map
611
For Master ADC, 0X100 for Slave ADC)
612
Table 119. ADC Register Map and Reset Values for each ADC
612
Common Registers) Offset =0X300)
614
Table 121. DAC Pins
617
Figure 138. Data Registers in Single DAC Channel Mode
618
Figure 139. Data Registers in Dual DAC Channel Mode
618
Figure 140. Timing Diagram for Conversion with Trigger Disabled TEN = 0
619
Table 122. DAC Trigger Selection
619
Figure 141. DAC LFSR Register Calculation Algorithm
621
Figure 142. DAC Conversion (SW Trigger Enabled) with LFSR Wave Generation
621
Figure 143. DAC Triangle Wave Generation
622
Figure 144. DAC Conversion (SW Trigger Enabled) with Triangle Wave Generation
622
Table 123. Sample and Refresh Timings
623
Figure 145. DAC Sample and Hold Mode Phase Diagram
625
Table 124. Channel Output Modes Summary
625
Table 125. Effect of Low-Power Modes on DAC
632
Table 126. DAC Register Map and Reset Values
646
Figure 146.DCMI Block Diagram
649
Figure 147.Top-Level Block Diagram
649
Figure 148.DCMI Signal Waveforms
650
Table 127. DCMI External Signals
650
Table 128. Positioning of Captured Data Bytes in 32-Bit Words (8-Bit Width)
651
Table 129. Positioning of Captured Data Bytes in 32-Bit Words (10-Bit Width)
651
Table 130. Positioning of Captured Data Bytes in 32-Bit Words (12-Bit Width)
651
Figure 149.Timing Diagram
652
Table 131. Positioning of Captured Data Bytes in 32-Bit Words (14-Bit Width)
652
Figure 150.Frame Capture Waveforms in Snapshot Mode
654
Figure 151.Frame Capture Waveforms in Continuous Grab Mode
655
Figure 152.Coordinates and Size of the Window after Cropping
655
Figure 153.Data Capture Waveforms
656
Figure 154.Pixel Raster Scan Order
657
Table 132.Data Storage in Monochrome Progressive Video Format
657
Table 133.Data Storage in RGB Progressive Video Format
658
Table 134.Data Storage in Ycbcr Progressive Video Format
658
Table 135. Data Storage in Ycbcr Progressive Video Format - y Extraction Mode
659
Table 136.DCMI Interrupts
659
Table 137.DCMI Register Map and Reset Values
671
Table 138. VREFBUF Buffer Modes
672
Table 139. VREFBUF Register Map and Reset Values
674
Figure 155. Comparators Block Diagram
676
Table 140. COMP1 Input Plus Assignment
676
Table 141. COMP1 Input Minus Assignment
676
Table 142. COMP2 Input Plus Assignment
677
Table 143. COMP2 Input Minus Assignment
677
Figure 156. Window Mode
678
Figure 157. Comparator Hysteresis
679
Figure 158. Comparator Output Blanking
679
Table 144. Comparator Behavior in the Low Power Modes
680
Table 145. Interrupt Control Bits
681
Table 146. COMP Register Map and Reset Values
686
Table 147. Operational Amplifier Possible Connections
688
Figure 159. Standalone Mode: External Gain Setting Mode
689
Figure 160. Follower Configuration
690
Figure 161. PGA Mode, Internal Gain Setting (X2/X4/X8/X16), Inverting Input Not Used
691
Figure 162. PGA Mode, Internal Gain Setting (X2/X4/X8/X16), Inverting Input Used for Filtering
692
Table 148. Operating Modes and Calibration
693
Table 149. Effect of Low-Power Modes on the OPAMP
694
Table 150. OPAMP Register Map and Reset Values
699
Table 151. DFSDM1 Implementation
702
Figure 163. Single DFSDM Block Diagram
703
Table 152. DFSDM External Pins
704
Table 153. DFSDM Internal Signals
704
Table 154. DFSDM Triggers Connection
704
Table 155. DFSDM Break Connection
705
Figure 164. Input Channel Pins Redirection
707
Figure 165. Channel Transceiver Timing Diagrams
709
Figure 166. Clock Absence Timing Diagram for SPI
710
Figure 167. Clock Absence Timing Diagram for Manchester Coding
711
Figure 168. First Conversion for Manchester Coding (Manchester Synchronization)
713
Figure 169. Dfsdm_Chydatinr Registers Operation Modes and Assignment
717
Figure 170. Example: Sinc3 Filter Response
719
For some FOSR Values
719
Table 156. Filter Maximum Output Resolution (Peak Data Values from Filter Output)
719
Output) for some IOSR Values and FOSR = 256 and Sinc3 Filter Type (Largest Data)
720
Table 157. Integrator Maximum Output Resolution
720
Table 158. DFSDM Interrupt Requests
728
Table 159. DFSDM Register Map and Reset Values
748
Figure 171. LCD Controller Block Diagram
759
Table 160. Example of Frame Rate Calculation
760
Figure 172. 1/3 Bias, 1/4 Duty
761
Figure 173. Static Duty Case 1
762
Figure 174. Static Duty Case 2
763
Figure 175. 1/2 Duty, 1/2 Bias
764
Figure 176. 1/3 Duty, 1/3 Bias
765
Figure 177. 1/4 Duty, 1/3 Bias
766
Figure 178. 1/8 Duty, 1/4 Bias
767
Table 161. Blink Frequency
768
Figure 179. LCD Voltage Control
770
Figure 180. Deadtime
771
Table 162. Remapping Capability
773
Figure 181. SEG/COM Mux Feature Example
776
Figure 182. Flowchart Example
777
Table 163. LCD Behavior in Low-Power Modes
778
Table 164. LCD Interrupt Requests
778
Table 165. LCD Register Map and Reset Values
785
Figure 183. TSC Block Diagram
789
Figure 184. Surface Charge Transfer Analog I/O Group Structure
790
Figure 185. Sampling Capacitor Voltage Variation
791
Table 166. Acquisition Sequence Summary
791
Figure 186. Charge Transfer Acquisition Sequence
792
Figure 187. Spread Spectrum Variation Principle
793
Table 167. Spread Spectrum Deviation Versus AHB Clock Frequency
793
Table 168. I/O State Depending on Its Mode and IODEF Bit Value
794
Table 169. Effect of Low-Power Modes on TSC
796
Table 170. Interrupt Control Bits
796
Table 171. TSC Register Map and Reset Values
805
Figure 188. RNG Block Diagram
808
Table 172. RNG Internal Input/Output Signals
808
Figure 189. Entropy Source Model
809
Table 173. RNG Interrupt Requests
813
Table 174. RNG Register Map and Reset Map
816
Figure 190. AES Block Diagram
818
Figure 191. ECB Encryption Mode
820
Figure 192. ECB Decryption Mode
821
Figure 193. CBC Mode Encryption
822
Figure 194. CBC Mode Decryption
822
Figure 195. Example of Suspend Mode Management
824
Figure 196. CTR Mode Encryption
825
Figure 197. CTR Mode Decryption
825
Figure 198. 32-Bit Counter + Nonce Organization
826
Figure 199. 128-Bit Block Construction According to the Data Type
832
Figure 200. 128-Bit Block Construction According to the Data Type (Continued)
833
Figure 201. Mode 1: Encryption with 128-Bit Key Length
834
Figure 202. Mode 2: Key Derivation with 128-Bit Key Length
834
Figure 203. Mode 3: Decryption with 128-Bit Key Length
835
Figure 204. Mode 4: Key Derivation and Decryption with 128-Bit Key Length
836
Figure 205. DMA Requests and Data Transfers During Input Phase (AES_IN)
837
Figure 206. DMA Requests During Output Phase (AES_OUT)
837
Table 175. Processing Time (in Clock Cycle)
838
Table 176. Processing Time (in Clock Cycle) for ECB, CBC and CTR
838
Table 177. Processing Time (in Clock Cycle) for GCM and CMAC
838
Table 178. AES Interrupt Requests
839
Table 179. AES Register Map
851
Figure 207. HASH Block Diagram
854
Table 180. HASH Internal Input/Output Signals
855
Figure 208. Message Data Swapping Feature
856
Table 181. Hash Processor Outputs
858
Figure 209. HASH Save/Restore Mechanism
861
Figure 210. HASH Interrupt Mapping Diagram
863
Table 182. HASH Interrupt Requests
864
Table 183. Processing Time (in Clock Cycle)
864
Table 184. HASH Register Map and Reset Values
875
Figure 211. Advanced-Control Timer Block Diagram
877
Figure 212. Counter Timing Diagram with Prescaler Division Change from 1 to 2
879
Figure 213. Counter Timing Diagram with Prescaler Division Change from 1 to 4
879
Figure 214. Counter Timing Diagram, Internal Clock Divided by 1
881
Figure 215. Counter Timing Diagram, Internal Clock Divided by 2
881
Figure 216. Counter Timing Diagram, Internal Clock Divided by 4
882
Figure 217. Counter Timing Diagram, Internal Clock Divided by N
882
Figure 218. Counter Timing Diagram, Update Event When ARPE=0 (Timx_Arr Not Preloaded)
883
Figure 219. Counter Timing Diagram, Update Event When ARPE=1 (Timx_Arr Preloaded)
883
Figure 220. Counter Timing Diagram, Internal Clock Divided by 1
885
Figure 221. Counter Timing Diagram, Internal Clock Divided by 2
885
Figure 222. Counter Timing Diagram, Internal Clock Divided by 4
886
Figure 223. Counter Timing Diagram, Internal Clock Divided by N
886
Figure 224. Counter Timing Diagram, Update Event When Repetition Counter Is Not Used
887
Figure 225. Counter Timing Diagram, Internal Clock Divided by 1, Timx_Arr = 0X6
888
Figure 226. Counter Timing Diagram, Internal Clock Divided by 2
889
Figure 227. Counter Timing Diagram, Internal Clock Divided by 4, Timx_Arr=0X36
889
Figure 228. Counter Timing Diagram, Internal Clock Divided by N
890
Figure 229. Counter Timing Diagram, Update Event with ARPE=1 (Counter Underflow)
890
Figure 230. Counter Timing Diagram, Update Event with ARPE=1 (Counter Overflow)
891
Figure 231. Update Rate Examples Depending on Mode and Timx_Rcr Register Settings
892
Figure 232. External Trigger Input Block
893
Figure 233. TIM1 ETR Input Circuitry
893
Figure 234. TIM8 ETR Input Circuitry
894
Figure 235. Control Circuit in Normal Mode, Internal Clock Divided by 1
895
Figure 236. TI2 External Clock Connection Example
896
Figure 237. Control Circuit in External Clock Mode 1
897
Figure 238. External Trigger Input Block
897
Figure 239. Control Circuit in External Clock Mode 2
898
Figure 240. Capture/Compare Channel (Example: Channel 1 Input Stage)
899
Figure 241. Capture/Compare Channel 1 Main Circuit
900
Figure 242. Output Stage of Capture/Compare Channel (Channel 1, Idem Ch. 2 and 3)
900
Figure 243. Output Stage of Capture/Compare Channel (Channel 4)
901
Figure 244. Output Stage of Capture/Compare Channel (Channel 5, Idem Ch. 6)
901
Figure 245. PWM Input Mode Timing
903
Figure 246. Output Compare Mode, Toggle on OC1
905
Figure 247. Edge-Aligned PWM Waveforms (ARR=8)
906
Figure 248. Center-Aligned PWM Waveforms (ARR=8)
907
Figure 249. Generation of 2 Phase-Shifted PWM Signals with 50% Duty Cycle
909
Figure 250. Combined PWM Mode on Channel 1 and 3
910
Figure 251. 3-Phase Combined PWM Signals with Multiple Trigger Pulses Per Period
911
Figure 252. Complementary Output with Dead-Time Insertion
912
Figure 253. Dead-Time Waveforms with Delay Greater than the Negative Pulse
912
Figure 254. Dead-Time Waveforms with Delay Greater than the Positive Pulse
913
Figure 255. Break and Break2 Circuitry Overview
915
Figure 256. Various Output Behavior in Response to a Break Event on BRK (OSSI = 1)
917
Figure 257. PWM Output State Following BRK and BRK2 Pins Assertion (OSSI=1)
918
Table 185. Behavior of Timer Outputs Versus BRK/BRK2 Inputs
918
Figure 258. PWM Output State Following BRK Assertion (OSSI=0)
919
Figure 259. Output Redirection
919
Figure 260. Clearing Timx Ocxref
920
Figure 261. 6-Step Generation, COM Example (OSSR=1)
921
Figure 262. Example of One Pulse Mode
922
Figure 263. Retriggerable One Pulse Mode
924
Figure 264. Example of Counter Operation in Encoder Interface Mode
925
Table 186. Counting Direction Versus Encoder Signals
925
Figure 265. Example of Encoder Interface Mode with TI1FP1 Polarity Inverted
926
Figure 266. Measuring Time Interval between Edges on 3 Signals
927
Figure 267. Example of Hall Sensor Interface
929
Figure 268. Control Circuit in Reset Mode
930
Figure 269. Control Circuit in Gated Mode
931
Figure 270. Control Circuit in Trigger Mode
932
Figure 271. Control Circuit in External Clock Mode 2 + Trigger Mode
933
Table 187. Timx Internal Trigger Connection
942
Table 188. Output Control Bits for Complementary Ocx and Ocxn Channels with Break Feature
956
Table 189. TIM1 Register Map and Reset Values
976
Table 190. TIM8 Register Map and Reset Values
979
Figure 272. General-Purpose Timer Block Diagram
983
Figure 273. Counter Timing Diagram with Prescaler Division Change from 1 to 2
985
Figure 274. Counter Timing Diagram with Prescaler Division Change from 1 to 4
985
Figure 275. Counter Timing Diagram, Internal Clock Divided by 1
986
Figure 276. Counter Timing Diagram, Internal Clock Divided by 2
987
Figure 277. Counter Timing Diagram, Internal Clock Divided by 4
987
Figure 278. Counter Timing Diagram, Internal Clock Divided by N
988
Figure 279. Counter Timing Diagram, Update Event When ARPE=0 (Timx_Arr Not Preloaded)
988
Figure 280. Counter Timing Diagram, Update Event When ARPE=1 (Timx_Arr Preloaded)
989
Figure 281. Counter Timing Diagram, Internal Clock Divided by 1
990
Figure 282. Counter Timing Diagram, Internal Clock Divided by 2
990
Figure 283. Counter Timing Diagram, Internal Clock Divided by 4
991
Figure 284. Counter Timing Diagram, Internal Clock Divided by N
991
Figure 285. Counter Timing Diagram, Update Event When Repetition Counter
992
Is Not Used
992
Figure 286. Counter Timing Diagram, Internal Clock Divided by 1, Timx_Arr=0X6
993
Figure 287. Counter Timing Diagram, Internal Clock Divided by 2
994
Figure 288. Counter Timing Diagram, Internal Clock Divided by 4, Timx_Arr=0X36
994
Figure 289. Counter Timing Diagram, Internal Clock Divided by N
995
Figure 290. Counter Timing Diagram, Update Event with ARPE=1 (Counter Underflow)
995
Figure 291. Counter Timing Diagram, Update Event with ARPE=1 (Counter Overflow)
996
Figure 292. Control Circuit in Normal Mode, Internal Clock Divided by 1
997
Figure 293. TI2 External Clock Connection Example
997
Figure 294. Control Circuit in External Clock Mode 1
998
Figure 295. External Trigger Input Block
999
Figure 296. Control Circuit in External Clock Mode 2
1000
Figure 297. Capture/Compare Channel (Example: Channel 1 Input Stage)
1001
Figure 298. Capture/Compare Channel 1 Main Circuit
1001
Figure 299. Output Stage of Capture/Compare Channel (Channel 1)
1002
Figure 300. PWM Input Mode Timing
1004
Figure 301. Output Compare Mode, Toggle on OC1
1006
Figure 302. Edge-Aligned PWM Waveforms (ARR=8)
1007
Figure 303. Center-Aligned PWM Waveforms (ARR=8)
1008
Figure 304. Generation of 2 Phase-Shifted PWM Signals with 50% Duty Cycle
1009
Figure 305. Combined PWM Mode on Channels 1 and 3
1011
Figure 306. Clearing Timx Ocxref
1012
Figure 307. Example of One-Pulse Mode
1013
Figure 308. Retriggerable One Pulse Mode
1015
Figure 309. Example of Counter Operation in Encoder Interface Mode
1016
Table 191. Counting Direction Versus Encoder Signals
1016
Figure 310. Example of Encoder Interface Mode with TI1FP1 Polarity Inverted
1017
Figure 311. Control Circuit in Reset Mode
1018
Figure 312. Control Circuit in Gated Mode
1019
Figure 313. Control Circuit in Trigger Mode
1020
Figure 314. Control Circuit in External Clock Mode 2 + Trigger Mode
1021
Figure 315. Master/Slave Timer Example
1021
Figure 316. Gating TIM2 with OC1REF of TIM3
1022
Figure 317. Gating TIM2 with Enable of TIM3
1023
Figure 318. Triggering TIM2 with Update of TIM3
1024
Figure 319. Triggering TIM2 with Enable of TIM3
1024
Figure 320. Triggering TIM3 and TIM2 with TIM3 TI1 Input
1025
Table 192. Timx Internal Trigger Connection
1032
Table 193. Output Control Bit for Standard Ocx Channels
1043
Table 194. TIM2/TIM3/TIM4/TIM5 Register Map and Reset Values
1050
Figure 321. TIM15 Block Diagram
1055
Figure 322. TIM16/TIM17 Block Diagram
1056
Figure 323. Counter Timing Diagram with Prescaler Division Change from 1 to 2
1058
Figure 324. Counter Timing Diagram with Prescaler Division Change from 1 to 4
1058
Figure 325. Counter Timing Diagram, Internal Clock Divided by 1
1060
Figure 326. Counter Timing Diagram, Internal Clock Divided by 2
1060
Figure 327. Counter Timing Diagram, Internal Clock Divided by 4
1061
Figure 328. Counter Timing Diagram, Internal Clock Divided by N
1061
Preloaded)
1062
Figure 331. Update Rate Examples Depending on Mode and Timx_Rcr Register Settings
1064
Figure 332. Control Circuit in Normal Mode, Internal Clock Divided by 1
1065
Figure 333. TI2 External Clock Connection Example
1065
Figure 334. Control Circuit in External Clock Mode 1
1066
Figure 335. Capture/Compare Channel (Example: Channel 1 Input Stage)
1067
Figure 336. Capture/Compare Channel 1 Main Circuit
1067
Figure 337. Output Stage of Capture/Compare Channel (Channel 1)
1068
Figure 338. Output Stage of Capture/Compare Channel (Channel 2 for TIM15)
1068
Figure 339. PWM Input Mode Timing
1070
Figure 340. Output Compare Mode, Toggle on OC1
1072
Figure 341. Edge-Aligned PWM Waveforms (ARR=8)
1073
Figure 342. Combined PWM Mode on Channel 1 and 2
1074
Figure 343. Complementary Output with Dead-Time Insertion
1075
Figure 344. Dead-Time Waveforms with Delay Greater than the Negative Pulse
1076
Figure 345. Dead-Time Waveforms with Delay Greater than the Positive Pulse
1076
Figure 346. Break Circuitry Overview
1078
Figure 347. Output Behavior in Response to a Break
1080
Figure 348. Example of One Pulse Mode
1081
Figure 349. Measuring Time Interval between Edges on 2 Signals
1083
Figure 350. Control Circuit in Reset Mode
1084
Figure 351. Control Circuit in Gated Mode
1085
Figure 352. Control Circuit in Trigger Mode
1086
Table 195. Timx Internal Trigger Connection
1093
(Tim15)
1102
Table 196. Output Control Bits for Complementary Ocx and Ocxn Channels with Break Feature
1102
Table 197. TIM15 Register Map and Reset Values
1110
(Tim16/17)
1122
Table 198. Output Control Bits for Complementary Ocx and Ocxn Channels with Break Feature
1122
Table 199. TIM16/TIM17 Register Map and Reset Values
1132
Figure 353. Basic Timer Block Diagram
1134
Figure 354. Counter Timing Diagram with Prescaler Division Change from 1 to 2
1136
Figure 355. Counter Timing Diagram with Prescaler Division Change from 1 to 4
1136
Figure 356. Counter Timing Diagram, Internal Clock Divided by 1
1137
Figure 357. Counter Timing Diagram, Internal Clock Divided by 2
1138
Figure 358. Counter Timing Diagram, Internal Clock Divided by 4
1138
Figure 359. Counter Timing Diagram, Internal Clock Divided by N
1139
Preloaded)
1139
Preloaded)
1140
Figure 362. Control Circuit in Normal Mode, Internal Clock Divided by 1
1141
Table 200. TIM6/TIM7 Register Map and Reset Values
1146
Table 201. Stm32L4Xx LPTIM Features
1147
Figure 363. Low-Power Timer Block Diagram
1148
Figure 364. Glitch Filter Timing Diagram
1149
Table 202. Prescaler Division Ratios
1150
And Set-Once Mode Activated (WAVE Bit Is Set)
1151
Figure 365. LPTIM Output Waveform, Single Counting Mode Configuration
1151
Figure 366. LPTIM Output Waveform, Single Counting Mode Configuration
1151
Figure 367. LPTIM Output Waveform, Continuous Counting Mode Configuration
1152
Figure 368. Waveform Generation
1154
Table 203. Encoder Counting Scenarios
1156
Figure 369. Encoder Mode Counting Sequence
1157
Table 204. Effect of Low-Power Modes on the LPTIM
1157
Table 205. LPTIM External Trigger Connection
1164
Table 206. LPTIM Register Map and Reset Values
1169
Figure 370. IR Internal Hardware Connections with TIM16 and TIM17
1170
Figure 371. Independent Watchdog Block Diagram
1171
Table 207. IWDG Register Map and Reset Values
1179
Figure 372. Watchdog Block Diagram
1181
Figure 373. Window Watchdog Timing Diagram
1182
Table 208. WWDG Register Map and Reset Values
1185
Table 209. RTC Pin PC13 Configuration
1189
Table 210. RTC_OUT Mapping
1190
Table 211. RTC Functions over Modes
1191
Table 212. Effect of Low-Power Modes on RTC
1203
Table 213. Interrupt Control Bits
1204
Table 214. RTC Register Map and Reset Values
1229
Table 215. Stm32L496Xx/4A6Xx Devices I2C Implementation
1232
Table 216. Stm32L475Xx/476Xx/486Xx Devices I2C Implementation
1232
Figure 375. I2C Block Diagram
1234
Figure 376. I2C Bus Protocol
1236
Table 217. Comparison of Analog Vs. Digital Filters
1237
Figure 377. Setup and Hold Timings
1238
Figure 378. I2C Initialization Flowchart
1241
Figure 379. Data Reception
1242
Figure 380. Data Transmission
1243
Table 219. I2C Configuration Table
1244
Figure 381. Slave Initialization Flowchart
1247
Figure 382. Transfer Sequence Flowchart for I2C Slave Transmitter, NOSTRETCH=0
1248
Figure 383. Transfer Sequence Flowchart for I2C Slave Transmitter, NOSTRETCH=1
1249
Figure 384. Transfer Bus Diagrams for I2C Slave Transmitter
1250
Figure 385. Transfer Sequence Flowchart for Slave Receiver with NOSTRETCH=0
1251
Figure 386. Transfer Sequence Flowchart for Slave Receiver with NOSTRETCH=1
1252
Figure 387. Transfer Bus Diagrams for I2C Slave Receiver
1252
Figure 388. Master Clock Generation
1254
Table 220. I2C-SMBUS Specification Clock Timings
1255
Figure 389. Master Initialization Flowchart
1256
Figure 390. 10-Bit Address Read Access with HEAD10R=0
1256
Figure 391. 10-Bit Address Read Access with HEAD10R=1
1257
Figure 392. Transfer Sequence Flowchart for I2C Master Transmitter for N≤255 Bytes
1258
Figure 393. Transfer Sequence Flowchart for I2C Master Transmitter for N>255 Bytes
1259
Figure 394. Transfer Bus Diagrams for I2C Master Transmitter
1260
Figure 395. Transfer Sequence Flowchart for I2C Master Receiver for N≤255 Bytes
1262
Figure 396. Transfer Sequence Flowchart for I2C Master Receiver for N >255 Bytes
1263
Figure 397. Transfer Bus Diagrams for I2C Master Receiver
1264
Table 221. Examples of Timings Settings for Fi2Cclk = 8 Mhz
1265
Table 222. Examples of Timings Settings for Fi2Cclk = 16 Mhz
1265
Table 223. Examples of Timings Settings for Fi2Cclk = 48 Mhz
1266
Table 224. Smbus Timeout Specifications
1268
Figure 398. Timeout Intervals for T
1269
Low:sext Low:mext
1269
Table 225. SMBUS with PEC Configuration
1270
(Max T TIMEOUT = 25 Ms)
1271
Table 228. Examples of TIMEOUTA Settings for Various I2CCLK Frequencies (Max T IDLE = 50 Μs)
1272
Figure 399. Transfer Sequence Flowchart for Smbus Slave Transmitter N Bytes + PEC
1273
Figure 400. Transfer Bus Diagrams for Smbus Slave Transmitter (SBC=1)
1273
Figure 401. Transfer Sequence Flowchart for Smbus Slave Receiver N Bytes + PEC
1275
Figure 402. Bus Transfer Diagrams for Smbus Slave Receiver (SBC=1)
1276
Figure 403. Bus Transfer Diagrams for Smbus Master Transmitter
1277
Figure 404. Bus Transfer Diagrams for Smbus Master Receiver
1279
Table 229. Effect of Low-Power Modes on the I2C
1283
Table 230. I2C Interrupt Requests
1284
Figure 405. I2C Interrupt Mapping Diagram
1285
Table 231. I2C Register Map and Reset Values
1300
Table 232. Stm32L4X5/Stm32L4X6 USART/UART/LPUART Features
1304
Figure 406. USART Block Diagram
1306
Figure 407. Word Length Programming
1308
Figure 408. Configurable Stop Bits
1310
Figure 409. TC/TXE Behavior When Transmitting
1311
Figure 410. Start Bit Detection When Oversampling by 16 or 8
1312
Figure 411. Data Sampling When Oversampling by 16
1316
Figure 412. Data Sampling When Oversampling by 8
1316
Table 233. Noise Detection from Sampled Data
1316
Oversampling by 16 or by 8
1319
Table 234. Error Calculation for Programmed Baud Rates at F
1319
Table 235. Tolerance of the USART Receiver When BRR [3:0] = 0000
1320
Table 236. Tolerance of the USART Receiver When BRR [3:0] Is Different from 0000
1321
Figure 413. Mute Mode Using Idle Line Detection
1323
Figure 414. Mute Mode Using Address Mark Detection
1324
Table 237. Frame Formats
1325
Figure 415. Break Detection in LIN Mode (11-Bit Break Length - LBDL Bit Is Set)
1327
Figure 416. Break Detection in LIN Mode Vs. Framing Error Detection
1328
Figure 417. USART Example of Synchronous Transmission
1329
Figure 418. USART Data Clock Timing Diagram (M Bits = 00)
1329
Figure 419. USART Data Clock Timing Diagram (M Bits = 01)
1330
Figure 420. RX Data Setup/Hold Time
1330
Figure 421. ISO 7816-3 Asynchronous Protocol
1332
Figure 422. Parity Error Detection Using the 1.5 Stop Bits
1333
Figure 423. Irda SIR ENDEC- Block Diagram
1337
Figure 424. Irda Data Modulation (3/16) -Normal Mode
1338
Figure 425. Transmission Using DMA
1339
Figure 426. Reception Using DMA
1340
Figure 427. Hardware Flow Control between 2 Usarts
1340
Figure 428. RS232 RTS Flow Control
1341
Figure 429. RS232 CTS Flow Control
1342
Table 238. Effect of Low-Power Modes on the USART
1344
Table 239. USART Interrupt Requests
1344
Figure 430. USART Interrupt Mapping Diagram
1345
Table 240. USART Register Map and Reset Values
1368
Figure 431. LPUART Block Diagram
1373
Figure 432. Word Length Programming
1375
Figure 433. Configurable Stop Bits
1376
Figure 434. TC/TXE Behavior When Transmitting
1378
Table 241. Error Calculation for Programmed Baud Rates at Fck = 32,768 Khz
1382
Table 242. Error Calculation for Programmed Baud Rates at Fck = 80 Mhz
1382
Table 243. Tolerance of the LPUART Receiver
1383
Figure 435. Mute Mode Using Idle Line Detection
1385
Figure 436. Mute Mode Using Address Mark Detection
1386
Table 244. Frame Formats
1386
Figure 437. Transmission Using DMA
1389
Figure 438. Reception Using DMA
1390
Figure 439. Hardware Flow Control between 2 Lpuarts
1390
Figure 440. RS232 RTS Flow Control
1391
Figure 441. RS232 CTS Flow Control
1392
Table 245. Effect of Low-Power Modes on the LPUART
1394
Table 246. LPUART Interrupt Requests
1395
Figure 442. LPUART Interrupt Mapping Diagram
1396
Table 247. LPUART Register Map and Reset Values
1411
Figure 443. SPI Block Diagram
1413
Table 248. Stm32L4X5/Stm32L4X6 SPI Implementation
1413
Figure 444. Full-Duplex Single Master/ Single Slave Application
1414
Figure 445. Half-Duplex Single Master/ Single Slave Application
1415
Figure 446. Simplex Single Master/Single Slave Application
1416
Slave in Receive-Only Mode)
1416
Figure 447. Master and Three Independent Slaves
1417
Figure 448. Multi-Master Application
1418
Figure 449. Hardware/Software Slave Select Management
1419
Figure 450. Data Clock Timing Diagram
1420
Figure 451. Data Alignment When Data Length Is Not Equal to 8-Bit or 16-Bit
1421
Figure 452. Packing Data in FIFO for Transmission and Reception
1425
Figure 453. Master Full-Duplex Communication
1428
Figure 454. Slave Full-Duplex Communication
1429
Figure 455. Master Full-Duplex Communication with CRC
1430
Figure 456. Master Full-Duplex Communication in Packed Mode
1431
Figure 457. NSSP Pulse Generation in Motorola SPI Master Mode
1434
Figure 458. TI Mode Transfer
1435
Table 249. SPI Interrupt Requests
1437
Table 250. SPI Register Map and Reset Values
1446
Table 251. SAI Internal Signals
1450
Table 252. SAI Pins
1450
Table 253. External Synchronization Selection
1452
Figure 460. Audio Frame
1453
Figure 461. FS Role Is Start of Frame + Channel Side Identification (FSDEF = TRIS = 1)
1455
Figure 462. FS Role Is Start of Frame (FSDEF = 0)
1456
Figure 463. Slot Size Configuration with FBOFF = 0 in Sai_Xslotr
1457
Figure 464. First Bit Offset
1457
Figure 465. Audio Block Clock Generator Overview
1458
Table 254. Example of Possible Audio Frequency Sampling Range
1459
Figure 466. AC'97 Audio Frame
1462
Embedded Sais (Three External AC'97 Decoders)
1463
Figure 467. Example of Typical AC'97 Configuration on Devices Featuring at Least
1463
Figure 468. SPDIF Format
1464
Figure 469. Sai_Xdr Register Ordering
1465
Table 255. SOPD Pattern
1465
Table 256. Parity Bit Calculation
1465
Table 257. Audio Sampling Frequency Versus Symbol Rates
1466
Figure 470. Data Companding Hardware in an Audio Block in the SAI
1468
Figure 471. Tristate Strategy on SD Output Line on an Inactive Slot
1470
Figure 472. Tristate on Output Data Line in a Protocol Like I2S
1471
Figure 473. Overrun Detection Error
1472
Figure 474. FIFO Underrun Event
1472
Table 258. SAI Interrupt Sources
1475
Table 259. SAI Register Map and Reset Values
1489
Figure 475. S1 Signal Coding
1491
Figure 476. S2 Signal Coding
1491
Figure 477. SWPMI Block Diagram
1493
Figure 479. SWP Frame Structure
1496
Figure 480. SWPMI no Software Buffer Mode Transmission
1497
Figure 482. SWPMI Multi Software Buffer Mode Transmission
1500
Figure 483. SWPMI no Software Buffer Mode Reception
1502
Figure 484. SWPMI Single Software Buffer Mode Reception
1503
Figure 486. SWPMI Single Buffer Mode Reception with CRC Error
1506
Table 260. Effect of Low-Power Modes on SWPMI
1507
Table 261. Interrupt Control Bits
1508
Table 262. Buffer Modes Selection for Transmission/Reception
1510
Table 263. SWPMI Register Map and Reset Values
1517
Figure 487. "No Response" and "No Data" Operations
1519
Figure 488. (Multiple) Block Read Operation
1519
Figure 489. (Multiple) Block Write Operation
1519
Figure 490. Sequential Read Operation
1520
Figure 491. Sequential Write Operation
1520
Figure 492. SDMMC Block Diagram
1520
Table 264. SDMMC I/O Definitions
1521
Figure 493. SDMMC Adapter
1522
Figure 494. Control Unit
1523
Figure 495. SDMMC_CK Clock Dephasing (BYPASS = 0)
1524
Figure 496. SDMMC Adapter Command Path
1524
Figure 497. Command Path State Machine (SDMMC)
1525
Figure 498. SDMMC Command Transfer
1526
Table 265. Command Format
1526
Table 266. Short Response Format
1527
Table 267. Long Response Format
1527
Table 268. Command Path Status Flags
1527
Figure 499. Data Path
1528
Table 269. Data Token Format
1530
Table 270. DPSM Flags
1531
Table 271. Transmit FIFO Status Flags
1532
Table 272. Receive FIFO Status Flags
1532
Table 273. Card Status
1543
Table 274. SD Status
1546
Table 275. Speed Class Code Field
1547
Table 276. Performance Move Field
1548
Table 277. AU_SIZE Field
1548
Table 278. Maximum AU Size
1548
Table 279. Erase Size Field
1549
Table 280. Erase Timeout Field
1549
Table 281. Erase Offset Field
1549
Table 282. Block-Oriented Write Commands
1552
Table 283. Block-Oriented Write Protection Commands
1553
Table 284. Erase Commands
1553
Table 285. I/O Mode Commands
1553
Table 286. Lock Card
1554
Table 287. Application-Specific Commands
1554
Table 288. R1 Response
1555
Table 289. R2 Response
1555
Table 290. R3 Response
1556
Table 291. R4 Response
1556
Table 292. R4B Response
1556
Table 293. R5 Response
1557
Table 294. R6 Response
1558
Table 295. Response Type and Sdmmc_Respx Registers
1564
Table 296. SDMMC Register Map
1574
Figure 501. CAN Network Topology
1577
Figure 502. Dual CAN Block Diagram
1578
Figure 503. Bxcan Operating Modes
1580
Figure 504. Bxcan in Silent Mode
1581
Figure 505. Bxcan in Loop Back Mode
1581
Figure 506. Bxcan in Combined Mode
1582
Figure 507. Transmit Mailbox States
1583
Figure 508. Receive FIFO States
1584
Figure 509. Filter Bank Scale Configuration - Register Organization
1587
Figure 510. Example of Filter Numbering
1588
Figure 511. Filtering Mechanism - Example
1589
Figure 512. CAN Error State Diagram
1590
Table 297. Transmit Mailbox Mapping
1590
Table 298. Receive Mailbox Mapping
1590
Figure 513. Bit Timing
1592
Figure 514. CAN Frames
1593
Figure 515. Event Flags and Interrupt Generation
1594
Figure 516. Can Mailbox Registers
1606
Table 299. Bxcan Register Map and Reset Values
1616
Table 300. OTG_FS Speeds Supported
1621
Table 301. USB_OTG Implementation for Stm32L4Xx
1624
Figure 517. OTG Full-Speed Block Diagram
1625
Figure 518. OTG_FS A-B Device Connection
1627
Figure 520. USB_FS Host-Only Connection
1633
Figure 521. SOF Connectivity (SOF Trigger Output to TIM and ITR1 Connection)
1637
Figure 522. Updating OTG_HFIR Dynamically
1639
Figure 523. Device-Mode FIFO Address Mapping and AHB FIFO Access Mapping
1640
Figure 524. Host-Mode FIFO Address Mapping and AHB FIFO Access Mapping
1641
Figure 525. Interrupt Hierarchy
1645
Table 302. Core Global Control and Status Registers (Csrs)
1646
Table 303. Host-Mode Control and Status Registers (Csrs)
1647
Table 304. Device-Mode Control and Status Registers
1648
Table 305. Data FIFO (DFIFO) Access Register Map
1650
Table 306. Power and Clock Gating Control and Status Registers
1650
Table 307. TRDT Values(FS)
1657
Table 308. Minimum Duration for Soft Disconnect
1694
Table 309. OTG_FS Register Map and Reset Values
1715
Figure 526. Transmit FIFO Write Task
1727
Figure 527. Receive FIFO Read Task
1728
Figure 528. Normal Bulk/Control OUT/SETUP
1729
Figure 529. Bulk/Control in Transactions
1733
Figure 530. Normal Interrupt out
1736
Figure 531. Normal Interrupt in
1740
Figure 532. Isochronous out Transactions
1742
Figure 533. Isochronous in Transactions
1745
Figure 534. Receive FIFO Packet Read
1750
Figure 535. Processing a SETUP Packet
1752
Figure 536. Bulk out Transaction
1758
Figure 537. TRDT Max Timing Case
1768
Figure 538. A-Device SRP
1769
Figure 539. B-Device SRP
1770
Figure 540. A-Device HNP
1771
Figure 541. B-Device HNP
1773
Figure 542. Block Diagram of STM32 MCU and Cortex ® -M4-Level Debug Support
1775
Figure 543. SWJ Debug Port
1777
Table 310. SWJ Debug Port Pins
1778
Table 311. Flexible SWJ-DP Pin Assignment
1778
Figure 544. JTAG TAP Connections
1781
Table 312. JTAG Debug Port Data Registers
1783
Table 313. 32-Bit Debug Port Registers Addressed through the Shifted Value A[3:2]
1784
Table 314. Packet Request (8-Bits)
1785
Table 315. ACK Response (3 Bits)
1786
Table 316. DATA Transfer (33 Bits)
1786
Table 317. SW-DP Registers
1787
Table 318. Cortex ® -M4 AHB-AP Registers
1788
Table 319. Core Debug Registers
1789
Table 320. Main ITM Registers
1791
Table 321. Main ETM Registers
1793
Figure 545. TPIU Block Diagram
1800
Table 322. Asynchronous TRACE Pin Assignment
1800
Table 323. Synchronous TRACE Pin Assignment
1801
Table 324. Flexible TRACE Pin Assignment
1801
Table 325. Important TPIU Registers
1805
Table 326. DBG Register Map and Reset Values
1807
Table 327. Document Revision History
1811
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ST STM32L4 5 Series Specifications
General
Brand
ST
Model
STM32L4 5 Series
Category
Microcontrollers
Language
English
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