ST STM32L4 5 Series - Figure 419. USART Data Clock Timing Diagram (M Bits = 01); Figure 420. RX Data Setup;Hold Time

Universal synchronous asynchronous receiver transmitter (USART) RM0351
1330/1830 DocID024597 Rev 5
Figure 419. USART data clock timing diagram (M bits = 01)
Figure 420. RX data setup/hold time
Note: The function of CK is different in Smartcard mode. Refer to Section 40.5.13: USART
Smartcard mode for more details.
06Y9
       
       




06%
06%
/6%
/6%6WDUW
6WDUW 6WRS
,GOHRU
SUHFHGLQJ
WUDQVPLVVLRQ
,GOHRUQH[W
WUDQVPLVVLRQ

/%&/ELWFRQWUROVODVWGDWDSXOVH
&DSWXUH
VWUREH
'DWDRQ5;
IURPVODYH
'DWDRQ7;
IURPPDVWHU
&ORFN&32/ 
&3+$ 
&ORFN&32/ 
&3+$ 
&ORFN&32/ 
&3+$ 
&ORFN&32/ 
&3+$ 
6WRS
0ELWV GDWDELWV


06Y9
'DWDRQ5;IURPVODYH
&.
FDSWXUHVWUREHRQ&.ULVLQJ
HGJHLQWKLVH[DPSOH
9DOLG'$7$ELW
W
6(783
W
+2/'
W
6(783
W
+2/'
ELWWLPH