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RM0351 Hash processor (HASH)
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Note: If the context swapping does not involve HMAC operations, the HASH_CSR38 to
HASH_CSR53 registers do not need to be saved and restored.
If the context swapping occurs between two blocks (the last block was completely
processed and the next block has not yet been pushed into the IN FIFO, NBW = 000 in the
HASH_CR register), the HASH_CSR22 to HASH_CSR37 registers do not need to be saved
and restored.
29.3.9 HASH DMA interface
The hash processor provides an interface to connect to the DMA controller. This DMA can
be used to write data to the HASH by setting the DMAE bit in the HASH_CR register. When
this bit is set, the HASH asserts the burst request signal to the DMA controller when there is
enough free words in the FIFO to support a burst of four words.
Once four 32-bit words have been received, the HASH automatically restarts this process,
checks the FIFO size, and asserts a new request if the FIFO status allow a burst reception.
For more information refer to Section 29.3.5: Message digest computing.
Before starting the DMA transfer, the software must program the number of valid bits in the
last word that will be copied into HASH_DIN register. This is done by writing in HASH_STR
register the following value:
NBLW = Len(Message)% 32
where “x%32” gives the remainder of x divided by 32.
DMAS bit in HASH_SR register provides information on the DMA interface activity. This bit
is set with DMAE and cleared when DMAE is cleared to 0 and no DMA transfer is ongoing.
Note: No interrupt is associated to DMAS bit.
29.3.10 HASH error management
No error flags are generated by the HASH hardware.
29.4 HASH interrupts
Two individual maskable interrupt sources are generated by the hash processor to signal
following events:
• Digest calculation completion (DCIS)
• Data input buffer ready (DINIS)
Both interrupt sources are connected to the same global interrupt request signal, as shown
on Figure 210.
Figure 210. HASH interrupt mapping diagram
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