DocID024597 Rev 5 1171/1830
RM0351 Independent watchdog (IWDG)
1179
36 Independent watchdog (IWDG)
36.1 Introduction
The devices feature an embedded watchdog peripheral that offers a combination of high
safety level, timing accuracy and flexibility of use. The Independent watchdog peripheral
detects and solves malfunctions due to software failure, and triggers system reset when the
counter reaches a given timeout value.
The independent watchdog (IWDG) is clocked by its own dedicated low-speed clock (LSI)
and thus stays active even if the main clock fails.
The IWDG is best suited for applications that require the watchdog to run as a totally
independent process outside the main application, but have lower timing accuracy
constraints. For further information on the window watchdog, refer to Section 37 on page
1180.
36.2 IWDG main features
• Free-running downcounter
• Clocked from an independent RC oscillator (can operate in Standby and Stop modes)
• Conditional Reset
– Reset (if watchdog activated) when the downcounter value becomes lower than
0x000
– Reset (if watchdog activated) if the downcounter is reloaded outside the window
36.3 IWDG functional description
36.3.1 IWDG block diagram
Figure 371 shows the functional blocks of the independent watchdog module.
Figure 371. Independent watchdog block diagram
1. The watchdog function is implemented in the V
CORE
voltage domain that is still functional in Stop and
Standby modes.
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