DocID024597 Rev 5 833/1830
RM0351 Advanced encryption standard hardware accelerator (AES)
852
Figure 200. 128-bit block construction according to the data type (continued)
28.9 Operating modes
28.9.1 Mode 1: encryption
1. Disable the AES by resetting EN bit in the AES_CR register.
2. Configure the mode 1 by programming MODE[1:0] = 00 in the AES_CR register and
select which type of chaining mode needs to be performed by programming the
CHMOD[2:0] bits.
3. Select key length 128-bits or 256-bits via KEYSIZE bits configuration in AES_CR
register.
4. Write the AES_KEYRx registers (128-bit or 256-bit with encryption key) and the
AES_IVRx registers if CTR, CBC or GCM mode is selected. For ECB mode, the
AES_IVRx register is not used.
5. Enable the AES by setting the EN bit in the AES_CR register.
6. Write the AES_DINR register 4 times to input the plain text (MSB first) as shown in
Figure 201: Mode 1: encryption with 128-bit key length.
7. Wait until the CCF flag is set in the AES_SR register.
8. Read the AES_DOUTR register 4 times to get the cipher text (MSB first) as shown in
Figure 201: Mode 1: encryption with 128-bit key length.
9. Repeat steps 6,7,8 to process all the blocks with the same encryption key.
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