ST STM32L4 5 Series User Manual

Inter-integrated circuit (I2C) interface RM0351
1276/1830 DocID024597 Rev 5
Figure 402. Bus transfer diagrams for SMBus slave receiver (SBC=1)
This section is relevant only when SMBus feature is supported. Please refer to Section 39.3:
I2C implementation.
In addition to I2C master transfer management (refer to Section 39.4.8: I2C master mode)
some additional software flowcharts are provided to support SMBus.
SMBus Master transmitter
When the SMBus master wants to transmit the PEC, the PECBYTE bit must be set and the
number of bytes must be programmed in the NBYTES[7:0] field, before setting the START
bit. In this case the total number of TXIS interrupts will be NBYTES-1. So if the PECBYTE
bit is set when NBYTES=0x1, the content of the I2C_PECR register is automatically
transmitted.
If the SMBus master wants to send a STOP condition after the PEC, automatic end mode
should be selected (AUTOEND=1). In this case, the STOP condition automatically follows
the PEC transmission.
069
([DPSOH60%XVVODYHUHFHLYHUE\WHV3(&
$GGUHVV 6
(9$''5,65FKHFN$''&2'(DQG',5SURJUDP1%<7(6 3(&%<7( 5(/2$' VHW$''5&)
(95;1(,65UGGDWD
(95;1(,65UGGDWD
(95;1(,65UG3(&
$ GDWD $ GDWD $
5;1(
3(& $
5;1(
3
OHJHQG
WUDQVPLVVLRQ
UHFHSWLRQ
6&/VWUHWFK
(9 (9 (9
(9
$''5 5;1(
1%<7(6
([DPSOH60%XVVODYHUHFHLYHUE\WHV3(&ZLWK$&.FRQWURO
5(/2$' 
$GGUHVV 6
(9$''5,65FKHFN$''&2'(DQG',5SURJUDP1%<7(6 3(&%<7( 5(/2$' VHW$''5&)
(95;1(7&5,65UGGDWDSURJUDP1$&. DQG1%<7(6 
(95;1(7&5,65UGGDWDSURJUDP1$&. 1%<7(6 DQG5(/2$' 
(95;1(7&5,65UG3(&
$
$''5
GDWD $ GDWD $
5;1(7&5
3(& $
5;1(7&5
3
OHJHQG
WUDQVPLVVLRQ
UHFHSWLRQ
6&/VWUHWFK
9(9(9(
5;1(
(9
1%<7(6



ST STM32L4 5 Series Specifications

General

Brand	ST
Model	STM32L4 5 Series
Category	Microcontrollers
Language	English